LX64EV-5F100I 查看數據表（PDF） - Lattice Semiconductor
零件编号
产品描述 (功能)
生产厂家
LX64EV-5F100I Datasheet PDF : 72 Pages
| |||
Lattice Semiconductor
Figure 2. GDX Block
GRP
GDX Block
32 bits
MUX
Control Select
Control Array
4 bits
8
8
8
2
Nibble 0
MUX and Register
Block (MRB)
0
ispGDX2 Family Data Sheet
sysIO Bank
OE
IN
OUT
4 bits
4 bits
8
2
MUX and Register
Block (MRB)
1
8
2
MUX and Register
Block (MRB)
2
OE
IN
OUT
OE
IN
OUT
4 bits
8
2
MUX and Register
Block (MRB)
3
OE
IN
OUT
16 bits
4
16 bits
4
16 bits
4
8
2
8
2
8
2
Nibble 1
MRBs 4-7
Nibble 2
MRBs 8-11
Nibble 3
MRBs 12-15
OE
IN
OUT
OE
IN
OUT
OE
IN
OUT
The output register of the MRB has a built-in bi-directional shift register capability. Each output register correspond-
ing to MRB “n”, receives data output from its two adjacent MRBs, MRB (n-1) and MRB (n+1), to provide shift regis-
ter capability. Like the output register, each input register of the MRB has built-in shift register capability. Each input
register can receive data from its two adjacent MRB input registers, to provide bi-directional shift register capability.
The chaining crosses GDX Block boundaries. The chain of input registers and the chain of output registers can be
combined as one shift register via the GRP.
5
Share Link: 