LX64EV-5F100I 查看數據表（PDF） - Lattice Semiconductor

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LX64EV-5F100I

High Performance Interfacing and Switching

Lattice Semiconductor 

Lattice Semiconductor

ispGDX2 Family Data Sheet

The four data inputs to the 4:1 MUX come from the GRP. The output of this MUX connects to the output register. A

fast feedback path from the MUX to the GRP allows wider MUXes to be built. Table 2 summarizes the various MUX

sizes and delay levels.

Table 2. MUX Size Versus Internal Delay

MUX Sizes

4:1

Up to 16:1

Up to 64:1

Up to 188:1 (with ispGDX2-256)

Levels of Internal GRP Delays

One Level

Two Levels

Three Levels

Four Levels

Figure 3. ispGDX2 Family MRB

MUX Select

Control Array Signals

Global

Signals

GDX

Control Array

4 2-4

24 2

OE

MUX

CK

Select

Global

Signals

CE

D/L

Q

ClK OE

Reg/Latch

CE

Set

VCC

Reset

TOE

Flags*

(FIFO, SERDES

or PLL)

From GRP

from

Out_Reg(n-1)

from

Out_Reg(n+1)

D/L

Q

ClK Out

Reg/Latch

CE

Set Reset

VCC

S/R

Global Resetb

to Out_Reg(n-1)

to Out_Reg(n+1)

To GRP

Delay

FIFO Out*

from IN_Reg(n-1)

from IN_Reg(n+1)

CK

CE

S/R

*Selected MRBs see Logic Signal Connection Table for details

D/L

Q

ClK Input

Reg/Latch

CE

Set

Reset

Global Resetb

to IN_Reg(n-1)

to IN_Reg(n+1)

Control Array

The control array generates control signals for the 16 MRBs within a GDX Block. The true and complement forms

of 32 inputs from the GRP are available in the control array. The 20 NAND terms can use any or all of these inputs

to form the control array outputs. Two AND terms are combined with a NOR term to form Set/Reset and OE sig-

nals. Figure 4 illustrates the control array.

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