LX64EV-5F100I 查看數據表（PDF） - Lattice Semiconductor

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LX64EV-5F100I

High Performance Interfacing and Switching

Lattice Semiconductor 

Lattice Semiconductor

Figure 5. ispGDX2-256 sysIO Banks

ispGDX2 Family Data Sheet

VCCO5

VREF5

GND

VCCO6

VREF6

GND

sysIO Bank 4

sysIO Bank 5

sysIO Bank 3

sysIO Bank 2

sysIO Bank 6

sysIO Bank 7

sysIO Bank 1

sysIO Bank 0

VCCO2

VREF2

GND

VCCO1

VREF1

GND

There are three classes of I/O interface standards implemented in the ispGDX2 devices. The first is the non-termi-

nated, single-ended interface; it includes the 3.3V LVTTL standard along with the 1.8V, 2.5V and 3.3V LVCMOS

interface standards. The slew rate and strength of these output buffers can be controlled individually. Additionally,

PCI 3.3, PCI-X and AGP-1X are all subsets of this interface type. The second interface class implemented is the

terminated, single-ended interface standard. This group of interfaces includes different versions of SSTL and HSTL

interfaces along with CTT and GTL+. Use of these I/O interfaces requires an additional VREF signal. At the system

level, a termination voltage, VTT, is also required. Typically, an output will be terminated to VTT at the receiving end

of the transmission line it is driving. The final types of interfaces implemented are the differential standards

LVPECL, LVDS and Bus LVDS. Table 3 shows the I/O standards supported by the ispGDX2 devices along with

nominal VCCO, VREF and VTT.

The ispGDX2 family also features 5V tolerant I/O. I/O banks with VCCO = 3.3V may have inputs driven to a maxi-

mum of 5.5V for easy interfacing with legacy systems. Up to 64 I/O pins per device may be driven by 5V inputs.

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