ISPLSI2032VE 查看數據表（PDF） - Lattice Semiconductor

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ISPLSI2032VE

3.3V In-System Programmable High Density SuperFAST™ PLD

Lattice Semiconductor 

ispLSI 2032VE Timing Model

Specifications ispLSI 2032VE

I/O Cell

Ded. In

I/O Pin

(Input)

#21

I/O Delay

#20

Reset

GRP

GRP

#22

#45

GLB

Feedback

Comb 4 PT Bypass #23

Reg 4 PT Bypass

#24

GLB Reg Bypass

#28

20 PT

XOR Delays

#25, 26, 27

GLB Reg

Delay

D

Q

RST

#29, 30,

31, 32

ORP

I/O Cell

ORP Bypass

#37

ORP

Delay

#36

#38,

39

I/O Pin

(Output)

Y0,1,2

GOE 0

#43, 44

#42

Control RE

PTs OE

#33, 34, CK

35

Derivations of tsu, th and tco from the Product Term Clock

tsu

= Logic + Reg su - Clock (min)

= (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))

= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)

2.0ns = (0.4 + 0.6 + 1.9) + (0.5) - (0.4 + 0.6 + 0.4)

th

= Clock (max) + Reg h - Logic

= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)

= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)

1.9ns = (0.4 + 0.6 + 2.3) + (1.5) - (0.4 + 0.6 + 1.9)

tco

= Clock (max) + Reg co + Output

= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)

= (#20 + #22 + #35) + (#31) + (#36 + #38)

5.2ns = (0.4 + 0.6 + 2.3) + (0.3) + (0.6 + 1.0)

Note: Calculations are based on timing specifications for the ispLSI 2032VE-300L.

Table 2-0042/2032VE

#40, 41

0491/2000

9

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