2064VE 查看數據表（PDF） - Lattice Semiconductor

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2064VE

3.3V In-System Programmable High Density SuperFAST™ PLD

Lattice Semiconductor 

Specifications ispLSI 2064VE

External Timing Parameters

Over Recommended Operating Conditions

PARAMETER

TEST 3

COND.

#

DESCRIPTION1

-280

-200

UNITS

MIN. MAX. MIN. MAX.

tpd1

A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass

— 3.5 — 4.5 ns

tpd2

A 2 Data Propagation Delay

— — — 7.0 ns

fmax

A

3 Clock Frequency with Internal Feedback 2

280 — 200 — MHz

fmax (Ext.)

fmax (Tog.)

—

4

Clock

Frequency

with

External

Feedback

(

1

tsu2 +

) tco1

— 5 Clock Frequency, Max. Toggle

— — 133 — MHz

— — 200 — MHz

tsu1

— 6 GLB Reg. Setup Time before Clock, 4 PT Bypass

— — 3.0 — ns

tco1

A 7 GLB Reg. Clock to Output Delay, ORP Bypass

— — — 3.5 ns

th1

— 8 GLB Reg. Hold Time after Clock, 4 PT Bypass

— — 0.0 — ns

tsu2

— 9 GLB Reg. Setup Time before Clock

— — 4.0 — ns

tco2

A 10 GLB Reg. Clock to Output Delay

— — — 4.5 ns

th2

— 11 GLB Reg. Hold Time after Clock

— — 0.0 — ns

tr1

A 12 Ext. Reset Pin to Output Delay

— — — 6.0 ns

trw1

— 13 Ext. Reset Pulse Duration

— — 4.0 — ns

tptoeen

B 14 Input to Output Enable

— — — 8.0 ns

tptoedis

C 15 Input to Output Disable

— — — 8.0 ns

tgoeen

B 16 Global OE Output Enable

— — — 5.0 ns

tgoedis

C 17 Global OE Output Disable

— — — 5.0 ns

twh

— 18 External Synchronous Clock Pulse Duration, High

— — 2.5 — ns

twl

— 19 External Synchronous Clock Pulse Duration, Low

— — 2.5 — ns

1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.

2. Standard 16-bit counter using GRP feedback.

3. Reference Switching Test Conditions section.

Table 2-0030A/2064VE

5

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