SY100S891JC 查看數據表（PDF） - Micrel
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SY100S891JC Datasheet PDF : 6 Pages
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Micrel, Inc.
5-BIT REGISTERED
TRANSCEIVER
SY100S891
SY100S891
FEATURES
DESCRIPTION
s 25Ω cut-off bus outputs
s 50Ω receiver outputs
s Transmit and receive registers with separate clocks
s 1500ps max. delay from CLK1 to Bus Outputs (BUS)
s 1500ps max. delay from CLK2 to Receiver Outputs (Q)
s Individual bus enable pins
s Internal 75KΩ input pull-down resistors
s Voltage and temperature compensation for improved
noise immunity
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Available in 28-pin PLCC package
The SY100S891 is a 5-bit registered transceiver
containing five bus transceivers with both transmit and
receive registers. The bus outputs (BUS0 – BUS4) are
specified for driving a 25 ohm bus and the receive outputs
(Q0 – Q4) are specified for driving a 50 ohm line. The
bus outputs have a normal high level output voltage and
a normal low level output voltage when the bus enable
(BUSEN0 – BUSEN4) is high. However, the output is
switched to a cut-off level when a bus-enable is low.
This cut-off level is sufficiently low that a relatively high
impedance is presented to the bus in order to minimize
reflections. There is one bus-enable for each bus driver;
a clock (CLK1) which is common to all five bus driver
registers; and a separate clock (CLK2) which is common
to all five receive registers. Data at the D inputs is clocked
to the Bus register by a positive transition of CLK1 and
data on the bus is clocked into the Receiver register by
a positive transition of CLK2. A high on the Master Reset
clears all registers.
PIN NAMES
Pin
BUSEN0–4
D0 – D4
CLK1
CLK2
MR
Q0 – Q4
BUS0–4
Function
Bus Enable Inputs
Data Inputs
Bus Driver Clock Input
Receive Register Clock
Master Reset
Bus Receive Outputs
Bus Outputs
M9999-032406
hbwhelp@micrel.com or (408) 955-1690
1
Rev.: F Amendment: /0
Issue Date: March 2006
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