DS10004Z-2/TR 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS10004Z-2/TR

5-Tap High-Speed Silicon Delay Line

Dallas Semiconductor -> Maxim Integrated 

NOTES:

1. All voltages are referenced to ground.

DS1004

2. VCC=5 volts and 25°C. Delay accuracy on both the rising and falling edges within tolerances given in

Table 1.

3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application

sensitive with respect to decoupling, layout, etc.

TEST CONDITIONS

INPUT:

Ambient Temperature:

Supply Voltage (VCC):

Input Pulse:

25°C ±=3°C

5.0V ±=0.1V

High = 3.0V ±=0.1V

Low = 0.0V ±=0.1V

Source Impedance:

Rise and Fall Time:

50 ohm max.

3.0 ns max. (measured between 0.6V and 2.4V)

Pulse Width:

Pulse Period:

Output Load

Capacitance:

500 ns

1 µs

15 pF

OUTPUT:

Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on

the rising and falling edge.

NOTE:

Above conditions are for test only and do not restrict the devices under other data sheet conditions.

TIMING DIAGRAM: DS1004 INPUT TO OUTPUTS

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