K6T1008C2C-F 查看數據表（PDF） - Samsung

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K6T1008C2C-F

128Kx8 bit Low Power CMOS Static RAM

Samsung 

K6T1008C2C Family

Document Title

128K x8 bit Low Power CMOS Static RAM

Revision History

Revision No.

0.0

History

Initial draft

0.1

First revision

- Seperate read and write at ICC, ICC1

ICC = ICC1 → Read : 15mA, Write : 35mA

1.0

Finalized

- Add 70ns speed bin for commercial product and 85ns speed

bin for industrial.

2.0

Revised

- Improved operating current

Add typical value.

ICC Read : 15mA → 10mA(Remove write current)

ICC2 : 90mA → 60mA

- Speed bin change

Remove 45ns from commercial part

Remove 55ns and 100ns from industrial part.

PRELIMINARY

CMOS SRAM

Draft Date

November 22, 1995

April 15, 1996

Remark

Design target

Preliminary

September 5, 1996

Final

November 5, 1997

Final

The attached data sheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

1

Revision 2.0

November 1997

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