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K7P401822B 查看數據表(PDF) - Samsung

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K7P401822B Datasheet PDF : 13 Pages
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K7P403622B
K7P401822B
128Kx36 & 256Kx18 SRAM
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
FEATURES
• 128Kx36 or 256Kx18 Organizations.
• 3.3V VDD, 2.5/3.3V VDDQ.
• LVTTL Input and Output Levels.
• Differential, PECL clock / Single ended or differential LVTTL
clock Inputs
• Synchronous Read and Write Operation.
• Registered Input and Registered Output.
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• JTAG Boundary Scan (subset of IEEE std. 1149.1).
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm).
Organization
Part Number
128Kx36
128Kx36
128Kx36
256Kx18
256Kx18
256Kx18
K7P403622B-HC25
K7P403622B-HC20
K7P403622B-HC16
K7P401822B-HC25
K7P401822B-HC20
K7P401822B-HC16
Maximum Access
Frequency Time
250MHz
2.5
200MHz
2.7
166MHz
3.0
250MHz
2.5
200MHz
2.7
166MHz
3.0
FUNCTIONAL BLOCK DIAGRAM
SA[0:16]
or [0:17]
K,K
Clock
Buffer
Read
Address
Register
17 or 18
Write
Address
Register
17 or 18
2:1
MUX
Dec.
Data Out
Memory Array
128Kx36
256Kx18
36 or 18
S/A Array
36 or 18
MUX0
36 or 18
36 or 18
WAY
SS
SW
Control
Register
Control
Logic
E
ZZ
OE
G
Internal
Clock
Generator
PIN DESCRIPTION
Pin Name
K, K
SAn
DQn
SS
SW
SWa
SWb
SWc
SWd
M1, M2
Pin Description
Differential Clocks
Synchronous Address Input
Bi-directional Data Bus
Synchronous Select
Synchronous Global Write Enable
Synchronous Byte a Write Enable
Synchronous Byte b Write Enable
Synchronous Byte c Write Enable
Synchronous Byte d Write Enable
Read Protocol Mode Pins (M1=VSS, M2=VDD)
Data Out
Register
36 or 18
36 or 18
DQ
Pin Name
ZZ
G
TCK
TMS
TDI
TDO
VDD
VDDQ
VSS
NC
Pin Description
Asynchronous Power Down
Asynchronous Output Enable
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
Power Supply
Output Power Supply
GND
No Connection
Data In
36 or 18
W/D
Array
36 or 18
Data In
Register
(2 stage)
36 or 18
XDIN
-2-
Jul. 2003
Rev 1.2

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