K7P401822B 查看數據表（PDF） - Samsung
零件编号
产品描述 (功能)
生产厂家
K7P401822B Datasheet PDF : 13 Pages
| |||
K7P403622B
K7P401822B
128Kx36 & 256Kx18 SRAM
FUNCTION DESCRIPTION
The K7P403622B and K7P401822B are 4,718,592 bit Synchronous Pipeline Mode SRAM devices. They are organized as 131,072
words by 36 bits for K7P403622B and 262,144 words by 18 bits for K7P401822B, fabricated using Samsung's advanced CMOS
technology.
Single differential PECL level K clocks or Single ended or differential LVTTL clocks are used to initiate read/write operation and all
internal operations are self-timed. At the rising edge of K clock, Addresses, Write Enables, Synchronous Select and Data Ins are reg-
istered internally. Data outs are updated from output registers at the next rising edge of K clock. An internal write data buffer allows
write data to follow one cycle after addresses and controls. The package is 119(7x17) Ball Grid Array with balls on a 1.27mm pitch.
Read Operation
During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is
read between first and second edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock.
During consecutive read operations where the address is the same, the data output must be held constant without any glitches. This
characteristic is because the SRAM will be read by devices that will operate slower than the SRAM frequency and will require multi-
ple SRAM cycles to perform a single read operation.
Write Operation(Late Write)
During write operations, addresses and controls are registered at the first rising edge of K clock and data inputs are registered at the
following rising edge of K clock. Write addresses and data inputs are stored in the data in registers until the next write operation, and
only at the next write opeation are data inputs fully written into SRAM array. Byte write operation is supported using SW[a:d] and the
timing of SW[a:d] is the same as the SW signal.
Bypass Read Operation
Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are
identical. For this case, data outputs are from the data in registers instead of SRAM array. Bypass read operation occurs on a byte to
byte basis. If only one byte is written during a write operation but a read operation is required on the same address, a partial bypass
read operation occurs since the new byte data is from the data in registers while the remaing bytes are from SRAM array.
Sleep Mode
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored
and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep
mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all
pending operations have completed, since any pending operation will not guaranteed once sleep mode is initiated. Normal opera-
tions can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.
Mode Control
There are two mode control select pins (M1 and M2) used to set the proper read protocol. This SRAM supports single clock pipelined
operating mode. For proper specified device operation, M1 must be connected to VSS and M2 must be connected to VDD. These
mode pins must be set at power-up and must not change during device operation.
Power-Up/Power-Down Supply Voltage Sequence
The following power-up supply voltage sequence is recommended: VSS, VDD, VDDQ, and VIN. VDD and VDDQ can be applied simulta-
neously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
-4-
Jul. 2003
Rev 1.2
Share Link: 