K7P401822B 查看數據表（PDF） - Samsung

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K7P401822B

128Kx36 & 256Kx18 Synchronous Pipelined SRAM

Samsung 

K7P403622B

K7P401822B

128Kx36 & 256Kx18 SRAM

TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (SS Controlled, G=Low)

1

2

3

4

5

6

7

8

K

SAn

SS

SW

SWx

DQn

tKHKH

tAVKH

tKHAX

tKHKL tKLKH

A1

A2

A3

A4

A5

A4

A6

A7

tSVKH

tKHSX

tWVKH

tKHWX

tWVKH

tKHWX

tWVKH

tKHWX

tKHQV

Q1

tKHQZ tDVKH tKHDX

Q2

D3

tKHDX

D4

tKHQX1

tKHQX

Q5

Q4

NOTE

1. D3 is the input data written in memory location A3.

2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the

last write cycle address.

TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (G Controlled, SS=Low)

K

SAn

1

2

tKHKH

A1

A2

3

4

5

6

7

8

A3

A4

A5

A4

A6

A7

G

SW

SWx

DQn

tGHQZ

Q1

Q2

D3

D4

tGLQV

tGLQX

Q5

Q4

NOTE

1. D3 is the input data written in memory location A3.

2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last

write cycle address.

-8-

Jul. 2003

Rev 1.2

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