K7P401823B 查看數據表（PDF） - Samsung
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K7P401823B Datasheet PDF : 13 Pages
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K7P403623B
K7P401823B
128Kx36 & 256Kx18 SRAM
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
FEATURES
• 128Kx36 or 256Kx18 Organizations.
• 3.3V VDD, 2.5/3.3V VDDQ.
• LVTTL 2.5/3.3V Input and Output Levels.
• Differential, PECL clock / Single ended or differential LVTTL
clock Inputs
• Synchronous Read and Write Operation
• Registered Input and Latched Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9 bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• JTAG 1149.1 Compatible Test Access port.
• 119(7x17) Pin Ball Grid Array Package(14mmx22mm).
Organiza-
tion
Part Number
128Kx36
256Kx18
K7P403623B-H65
K7P403623B-H70
K7P403623B-H75
K7P401823B-H65
K7P401823B-H70
K7P401823B-H75
Cycle
Time
6
6.5
7
6
6.5
7
Access
Time
6.5
7.0
7.5
6.5
7.0
7.5
FUNCTIONAL BLOCK DIAGRAM
SA[0:16] or SA[0:17]
CK
SS
SW
SWx
(x=a, b, c, d)
or (x=a, b)
Latch
Latch
SW
Register
SWx
Register
SS
Register
Read
Address
Register
SW
Register
SWx
Register
SS
Register
1
Write
Address
0
Register
128Kx36
or
256Kx18
Array
Column Decoder
Write/Read Circuit
01
Data In
Register
Data Out
Latch
G
ZZ
K
CK
K
DQx[1:9]
(x=a, b, c, d)
or (x=a, b)
PIN DESCRIPTION
Pin Name
K, K
SAn
DQn
SW
SWa
SWb
SWc
SWd
ZZ
VDD
Pin Description
Differential Clocks(PECL or LVTTL Level)
Synchronous Address Input
Bi-directional Data Bus
Synchronous Global Write Enable
Synchronous Byte a Write Enable
Synchronous Byte b Write Enable
Synchronous Byte c Write Enable
Synchronous Byte d Write Enable
Asynchronous Power Down
Core Power Supply
Pin Name
VDDQ
M1, M2
G
SS
TCK
TMS
TDI
TDO
VSS
NC
Pin Description
Output Power Supply
Read Protocol Mode Pins ( M1=VDD, M2=VSS )
Asynchronous Output Enable
Synchronous Select
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
GND
No Connection
Jul. 2003
-2-
Rev 1.1
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