K7P401823B 查看數據表（PDF） - Samsung

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K7P401823B

128Kx36 & 256Kx18 Synchronous Pipelined SRAM

Samsung 

K7P403623B

K7P401823B

128Kx36 & 256Kx18 SRAM

TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES

K

SAn

SS

SW

SWx

G

DQn

1

2

3

4

5

6

7

8

9

tKHKH

tAVKH

tKHAX

A1

A1

tSVKH

tKHSX

tKHKL tKLKH

A2

A3

A4

A5

A4

A6

A7

tWVKH

tKHWX

tWVKH

tKHWX

tWVKH

tKHWX

tKLQV

tKHQV

tGHQZ

tGLQX

tGLQV

tKLQV

tKLQX

tKHQZ tDVKH tKHDX

tKLQX1

tKLQV tKHQZ

Q1

Q2

D3

D4

Q5

Q4

tKLQX1

NOTE

1. D3 is the input data written in memory location A3.

2. Q4 is the output data read from the write data buffer(not from the cell array), as a result of address A4 being a match from the last write

cycle address.

3. Data is valid at the output at the later of tKHQV following the rising clock edge, or tKLQV following the fallowing clock edge.

4. When SS is sampled high or SW is sampled low on the rising edge of clock, the outputs go into Hi-Z state no later than tKHQZ following

the rising clock edge.

5. When SS is low and SW is high on the rising edge of clock, the outputs go into Low-Z state(being driven) no earlier than tKLQX1 following

the next falling edge of clock.

6. When the SRAM is deselected, the output goes Hi-Z at tKHQZ following the rising clock edge. On the next read cycle, note that the

SRAM output do not leave the Hi-Z state until tKLQX1 after the falling clock edge.

Jul. 2003

-8-

Rev 1.1

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