K7R161884B-FC20(2004) 查看數據表（PDF） - Samsung
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K7R161884B-FC20 Datasheet PDF : 18 Pages
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K7R163684B
K7R161884B
512Kx36 & 1Mx18 QDRTM II b4 SRAM
AC TIMING CHARACTERISTICS(VDD=1.8V±0.1V, TA=0°C to +70°C)
PARAMETER
SYMBOL
Clock
Clock Cycle Time (K, K, C, C)
tKHKH
Clock Phase Jitter (K, K, C, C)
tKC var
Clock High Time (K, K, C, C)
tKHKL
Clock Low Time (K, K, C, C)
tKLKH
Clock to Clock (K↑ → K↑, C↑ → C↑)
tKHKH
Clock to data clock (K↑ → C↑, K↑→ C↑)
tKHCH
DLL Lock Time (K, C)
tKC lock
K Static to DLL reset
tKC reset
Output Times
C, C High to Output Valid
tCHQV
C, C High to Output Hold
tCHQX
C, C High to Echo Clock Valid
tCHCQV
C, C High to Echo Clock Hold
tCHCQX
CQ, CQ High to Output Valid
tCQHQV
CQ, CQ High to Output Hold
tCQHQX
C, High to Output High-Z
tCHQZ
C, High to Output Low-Z
tCHQX1
Setup Times
Address valid to K rising edge
tAVKH
Control inputs valid to K rising edge tIVKH
Data-in valid to K, K rising edge
tDVKH
Hold Times
K rising edge to address hold
tKHAX
K rising edge to control inputs hold tKHIX
K, K rising edge to data-in hold
tKHDX
-30
MIN MAX
3.30 5.25
0.20
1.32
1.32
1.49
0.00 1.45
1024
30
0.45
-0.45
0.45
-0.45
0.27
-0.27
0.45
-0.45
0.40
0.40
0.30
0.40
0.40
0.30
-25
MIN MAX
4.00 6.30
0.20
1.60
1.60
1.80
0.00 1.80
1024
30
0.45
-0.45
0.45
-0.45
0.30
-0.30
0.45
-0.45
0.50
0.50
0.35
0.50
0.50
0.35
-20
MIN MAX
5.00 7.88
0.20
2.00
2.00
2.20
0.00 2.30
1024
30
0.45
-0.45
0.45
-0.45
0.35
-0.35
0.45
-0.45
0.60
0.60
0.40
0.60
0.60
0.40
-16
UNIT NOTE
MIN MAX
6.00
2.40
2.40
2.70
0.00
1024
30
8.40 ns
0.20 ns 5
ns
ns
ns
2.80 ns
cycle 6
ns
0.50 ns 3
-0.50
ns 3
0.50 ns
-0.50
ns
0.40 ns 7
-0.40
ns 7
0.50 ns 3
-0.50
ns 3
0.70
ns
0.70
ns 2
0.50
ns
0.70
ns
0.70
ns
0.50
ns
Notes: 1. All address inputs must meet the specified setup and hold times for all latching clock edges.
2. Control singles are R, W,BW0,BW1 and (NW0, NW1, for x8) and (BW2, BW3, also for x36)
3. If C,C are tied high, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.
The specs as shown do not imply bus contention beacuse tCHQX1 is a MIN parameter that is worst case at totally different test conditions
(0°C, 1.9V) than tCHQZ, which is a MAX parameter(worst case at 70°C, 1.7V)
It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
7. Echo clock is very tightly controlled to data valid/data hold. By design, there is a ± 0.1 ns variation from echo clock to data.
The data sheet parameters reflect tester guardbands and test setup variations.
- 11 -
July. 2004
Rev 3.1
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