K7R161884B 查看數據表（PDF） - Samsung
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K7R161884B Datasheet PDF : 19 Pages
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K7R163684B
K7R161884B
512Kx36 & 1Mx18 QDRTM II b4 SRAM
WRITE OPERATIONS
Write cycles are initiated by activating W at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with K clock.
For 4-bit burst DDR operation, it will write four 36-bit or 18-bit or 8-bit data words with each write command.
The first “late” data is transferred and registered in to the device synchronous with next K clock rising edge.
Next burst data is transferred and registered synchronous with following K clock rising edge.
The process continues until all four data are transferred and registered.
Continuous write operations are initiated with K rising edge.
And “late writed” data is presented to the device on every rising edge of both K and K clocks.
The device disregards input data presented on the same cycle W disabled.
When the W is disabled after a read operation, the K7R163684B and K7R161884B will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
The K7R163684B and K7R161884B support byte write operations.
With activating BW0 or BW1 (BW2 or BW3) in write cycle, only one byte of input data is presented.
In K7R161884B, BW0 controls write operation to D0:D8, BW1 controls write operation to D9:D17.
And in K7R163684B BW2 controls write operation to D18:D26, BW3 controls write operation to D27:D35.
PROGRAMMABLE IMPEDANCE OUTPUT BUFFER OPERATION
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor (RQ).
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250Ω resistor will give an output impedance of 50Ω.
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time “push-outs”
or other anomalous behavior in the SRAM.
There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up,
the SRAM needs 1024 non-read cycles.
SINGLE CLOCK MODE
The K7R163684B and K7R161884B can be operated with the single clock pair K and K,
instead of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high
during operation.
After power up, this device can’t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
DEPTH EXPANSION
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently
and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.
POWER-UP/POWER-DOWN SUPPLY VOLTAGE SEQUENCING
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Rev. 5.0 July 2006
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