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K7R161884B 查看數據表(PDF) - Samsung

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K7R161884B Datasheet PDF : 19 Pages
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K7R163684B
K7R161884B
512Kx36 & 1Mx18 QDRTM II b4 SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
D
Q
K
RW
OPERATION
D(A1) D(A2) D(A3) D(A4) Q(A1) Q(A2) Q(A3) Q(A4)
Stopped X
X
Previous Previous Previous Previous Previous Previous Previous Previous
state
state
state
state
state
state
state
state
Clock Stop
H
H
X
X
X
X
High-Z High-Z High-Z High-Z No Operation
L4
X
X
X
X
X
DOUT
DOUT
DOUT
DOUT
at C(t+1) at C(t+2) at C(t+2) at C(t+3)
Read
H5
L4
Din
Din
Din
Din
at K(t+1) at K(t+1) at K(t+2) at K(t+2)
X
X
X
X
Write
Notes: 1. X means “Dont Care”.
2. The rising edge of clock is symbolized by ( ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
4. This signal was HIGH on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecutive K clock rising edges
is not permitted. The device will ignore the second request.
5. If this signal was LOW to initiated the previous cycle, this signal becomes a dont care for this operation however it is strongly recommended
that this signal is brought HIGH as shown in the truth table.
WRITE TRUTH TABLE(x18)
K
K
BW0
BW1
L
L
OPERATION
WRITE ALL BYTEs ( K↑ )
L
L
L
H
L
H
WRITE ALL BYTEs ( K↑ )
WRITE BYTE 0 ( K↑ )
WRITE BYTE 0 ( K↑ )
H
L
WRITE BYTE 1 ( K↑ )
H
L
H
H
H
H
WRITE BYTE 1 ( K↑ )
WRITE NOTHING ( K↑ )
WRITE NOTHING ( K↑ )
Notes: 1. X means “Dont Care”.
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ).
3. Assumes a WRITE cycle was initiated.
4. This table illustrates operation for x18 devices.
WRITE TRUTH TABLE(x36)
K
K
BW0
BW1
BW2
BW3
OPERATION
L
L
L
L
WRITE ALL BYTEs ( K↑ )
L
L
L
L
WRITE ALL BYTEs ( K↑ )
L
H
H
H
WRITE BYTE 0 ( K↑ )
L
H
H
H
WRITE BYTE 0 ( K↑ )
H
L
H
H
WRITE BYTE 1 ( K↑ )
H
L
H
H
WRITE BYTE 1 ( K↑ )
H
H
L
L
WRITE BYTE 2 and BYTE 3 ( K↑ )
H
H
L
L
WRITE BYTE 2 and BYTE 3 ( K↑ )
H
H
H
H
WRITE NOTHING ( K↑ )
H
H
H
H
WRITE NOTHING ( K↑ )
Notes: 1. X means “Dont Care”.
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ).
3. Assumes a WRITE cycle was initiated.
Rev. 5.0 July 2006
-9-

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