K7P323666M-H(G)C30 查看數據表（PDF） - Samsung
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K7P323666M-H(G)C30 Datasheet PDF : 14 Pages
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K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
1Mx36 & 2Mx18 Synchronous Pipelined SRAM
FEATURES
• 1Mx36 or 2Mx18 Organizations.
• 2.5V Core/1.5V Output Power Supply (1.9V max VDDQ).
• HSTL Input and Output Levels.
• Differential, HSTL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• Programmable Impedance Output Drivers.
• JTAG 1149.1 Compatible Test Access port.
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm).
Org.
Part Number
1Mx36
2Mx18
K7P323666M-H(G)C30
K7P323666M-H(G)C25
K7P321866M-H(G)C30
K7P321866M-H(G)C25
* G : Lead free package
Maximum Access
Frequency Time
300MHz
1.6
250MHz
2.0
300MHz
1.6
250MHz
2.0
FUNCTIONAL BLOCK DIAGRAM
SA[0:19] or SA[0:20]
CK
SS
SW
SWx
(x=a, b, c, d)
or (x=a, b)
Latch
Latch
SW
Register
SWx
Register
SS
Register
Read
Address
Register
SW
Register
SWx
Register
SS
Register
1
Write
Address
0
Register
G
ZZ
K
CK
K
1Mx36
or
2Mx18
Array
Column Decoder
Write/Read Circuit
01
Data In
Register
Data Out
Register
DQx[1:9]
(x=a, b, c, d)
or (x=a, b)
PIN DESCRIPTION
Pin Name
K, K
SAn
DQn
SW
SWa
SWb
SWc
SWd
ZZ
VDD
VDDQ
Pin Description
Differential Clocks
Synchronous Address Input
Bi-directional Data Bus
Synchronous Global Write Enable
Synchronous Byte a Write Enable
Synchronous Byte b Write Enable
Synchronous Byte c Write Enable
Synchronous Byte d Write Enable
Asynchronous Power Down
Core Power Supply
Output Power Supply
Pin Name
VREF
M1, M2
G
SS
TCK
TMS
TDI
TDO
ZQ
VSS
NC
Pin Description
HSTL Input Reference Voltage
Read Protocol Mode Pins ( M1=VSS, M2=VDDQ )
Asynchronous Output Enable
Synchronous Select
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
Output Driver Impedance Control
GND
No Connection
Dec. 2005
-3-
Rev 1.2
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