K7P323666M 查看數據表（PDF） - Samsung
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K7P323666M Datasheet PDF : 14 Pages
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K7P323666M
K7P321866M
1Mx36 & 2Mx18 SRAM
TRUTH TABLE
K ZZ G SS SW SWa SWb SWc SWd DQa DQb DQc DQd
Operation
X
H
X
X
X
X
X
X
X Hi-Z Hi-Z Hi-Z Hi-Z Power Down Mode. No Operation
X
L
H
X
X
X
X
X
X Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled.
↑
L
L
H
X
X
X
X
X Hi-Z Hi-Z Hi-Z Hi-Z Output Disabled. No Operation
↑
L
L
L
H
X
X
X
X DOUT DOUT DOUT DOUT Read Cycle
↑
L
X
L
L
H
H
H
H Hi-Z Hi-Z Hi-Z Hi-Z No Bytes Written
↑
L
X
L
L
L
H
H
H DIN Hi-Z Hi-Z Hi-Z Write first byte
↑
L
X
L
L
H
L
H
H Hi-Z DIN Hi-Z Hi-Z Write second byte
↑
L
X
L
L
H
H
L
H Hi-Z Hi-Z DIN Hi-Z Write third byte
↑
L
X
L
L
H
H
H
L Hi-Z Hi-Z Hi-Z DIN Write fourth byte
↑
L
X
L
L
L
L
L
L DIN DIN DIN DIN Write all bytes
NOTE : K & K are complementary
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Core Supply Voltage Relative to VSS
VDD
-0.5 to 3.13
V
Output Supply Voltage Relative to VSS
VDDQ
-0.5 to 2.4
V
Voltage on any I/O pin Relative to VSS
VIN
-0.5 to VDDQ+0.5 (2.4V MAX)
V
Output Short-Circuit Current
IOUT
25
mA
Operating Temperature
Storage Temperature
TOPR
TSTG
0 to 70
°C
-55 to 125
°C
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Core Power Supply Voltage
VDD
2.37
2.5
2.63
V
Output Power Supply Voltage
VDDQ
1.4
1.5
1.9
V
Input High Level
VIH
VREF+0.1
-
VDDQ+0.3
V
Input Low Level
VIL
-0.3
-
VREF-0.1
V
Input Reference Voltage
VREF
0.6
0.75
0.9
V
Clock Input Signal Voltage
VIN-CLK
-0.3
-
VDDQ+0.3
V
Clock Input Differential Voltage
VDIF-CLK
0.1
-
VDDQ+0.6
V
Clock Input Common Mode Voltage
VCM-CLK
0.6
0.75
0.9
V
Note
1, 2
1, 3
1, 4
1, 5
1, 6
NOTE : 1. These are DC test criteria. DC design criteria is VREF±50mV. The AC VIH/VIL levels are defined separately for measuring timing
parameters.
2. VIH (Max)DC=VDDQ+0.3, VIH (Max)AC=VDDQ+0.85V(pulse width ≤ 3ns).
3. VIL (Min)DC=-0.3V, VIL (Min)AC=-1.5V(pulse width ≤ 3ns).
4. VIN-CLK specifies the maximum allowable DC level for the differential clock. i.e VIL-CLK and VIH-CLK.
5. VDIF-CLK specifies the minimum Clock differential voltage required for switching. i.e DC voltage difference between VIL-CLK and VIH-CLK.
6. VCM-CLK specifies the Clock crossing point for the differential clock or the allowable common clock level for a single ended clock.
Dec. 2005
-6-
Rev 1.2
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