K7P161866A 查看數據表（PDF） - Samsung
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K7P161866A Datasheet PDF : 14 Pages
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K7P163666A
K7P161866A
512Kx36 & 1Mx18 SRAM
FUNCTION DESCRIPTION
The K7P163666A and K7P161866A are 18,874,368 bit Dual Mode (supports both Register Register and Late Select Mode) SRAM
devices. They are organized as 524,288 words by 36 bits for K7P163666A and 1,048,576 words by 18 bits for K7P161866A, fabri-
cated using Samsung's advanced CMOS technology. Late Write/Pipelined Read(RR) for x36/x18 organizations and Late Write/Late
Select Read(LS) for x36 organization are supported.
The chip is operated with a single +2.5V power supply and is compatible wtih HSTL input and output. The package is 119(7x17)
Plastic Ball Grid Array with balls on a 1.27mm pitch.
Read Operation for Register Register Mode(x36 and x18)
During read operations, addresses and controls are registered during the first rising edge of K clock and then the internal array is
read between first and second edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock.
Read Operation for Late Select Mode(x36)
During read operations, addresses(SA) and controls except the Way Select Address(SAS) are registered during the first rising edge
of K clock. The internal array(x72 bit data) is read between the first edge and the second edge, and as the Way Select Address(SAS)
is registered at the second clock edge, x36 bit data is mux selected before the output register.
Write Operation(Late Write)
During write operations, addresses including the Way Select Address(SAS) and controls are registered at the first rising edge of K
clock and data inputs are registered at the following rising edge of K clock. Write addresses and data inputs are stored in the data in
registers until the next write operation, and only at the next write opeation are data inputs fully written into SRAM array. Byte write
operation is supported using SW[a:d] and the timing of SW[a:d] is the same as the SW signal.
Bypass Read Operation
Since write data is not fully written into the array on first write cycle, there is a need to sense the address in case a future read is to be
done from the location that has not been written yet. For this case, the address comparator check to see if the new read address is
the same as the contents of the stored write address Latch. If the contents match, the read data must be supplied from the stored
write data latch with standard read timing. If there is no match, the read data comes from the SRAM array. The bypassing of the
SRAM array occurs on a byte by byte basis. If one byte is written and the other bytes are not, read data from the last written will have
new byte data from the write data buffer and the other bytes from the SRAM array.
Programmable Impedance Output Buffer Operation
This HSTL Late Write SRAM has been designed with programmable impedance output buffers. The SRAMs output buffer impedance
can be adjusted to match the system data bus impedance, by connecting a external resistor (RQ) between the ZQ pin of the SRAM
and VSS. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. For example, a 250Ω
resistor will give an output buffer impedance of 50Ω. The allowable range of RQ is from 175Ω to 350Ω. Internal circuits evaluate and
periodically adjust the output buffer impedance, as the impedance is affected by drifts in supply voltage and temperature. One evalu-
ation occurs every 32 clock cycles, with each evaluation moving the output buffer impedance level only one step at a time toward the
optimum level. Impedance updates occur when the SRAM is in High-Z state, and thus are triggered by write and deselect operations.
Updates will also be triggered with G HIGH initiated High-Z state, providing the specified G setup and hold times are met. Impedance
match is not instantaneous upon power-up. In order to guarantee optimum output driver impedance, the SRAM requires a minimum
number of non-read cycles (1,024) after power-up. The output buffers can also be programmed in a minimum impedance configura-
tion by connecting ZQ to VSS or VDD.
Mode Control
There are two mode control select pins (M1 and M2) used to set the proper read protocol. This SRAM supports single clock pipelined
operating mode. For proper specified device operation, M1 must be connected to VSS and M2 must be connected to VDD. These
mode pins must be set at power-up and must not change during device operation.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
Sleep Mode
Sleep mode is a low power mode initiated by bringing the asynchronous ZZ pin high. During sleep mode, all other inputs are ignored
and outputs are brought to a High-Impedance state. Sleep mode current and output High-Z are guaranteed after the specified sleep
mode enable time. During sleep mode the memory array data content is preserved. Sleep mode must not be initiated until after all
pending operations have completed, as any pending operation is not guaranteed to properly complete after sleep mode is initiated.
Normal operations can be resumed by bringing the ZZ pin low, but only after the specified sleep mode recovery time.
Sep. 2003
-5-
Rev 0.3
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