MU9C1485A-50TCI 查看數據表（PDF） - Music Semiconductors
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MU9C1485A-50TCI Datasheet PDF : 28 Pages
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WidePort LANCAM® Family
OPERATIONAL CHARACTERISTICS Continued
Cycle Type /E
Cmd Write L
Cmd Read L
Data Write L
Data Read L
H
/CM /W
LL
LH
HL
HH
XX
I/O Status SPS SPD TCO
IN
IN
ü
IN
ü
IN
ü
IN
ü
IN
ü
IN
OUT
ü
OUT
ü
OUT
OUT
ü
OUT
ü
OUT
ü
OUT
ü
OUT
ü
HIGH-Z
IN
ü
IN
ü
IN
ü
IN
ü
IN
ü
IN
ü
IN
OUT
ü
OUT
ü
OUT
ü
OUT
ü
OUT
ü
HIGH-Z
HIGH-Z
Operation
Load Instruction decoder
Load Address register
Load Control register
Load Page Address register
Load Segment Control register
Load Device Select register
Deselected
Read Next Free Address register
Read Address register
Read Status Register bits 31–0
Read Control register
Read Page Address register
Read Segment Control register
Read Device Select register
Read Current Persistent Source or Destination
Deselected
Load Comparand register
Load Mask Register 1
Load Mask Register 2
Write Memory Array at address
Write Memory Array at Next Free address
Write Memory Array at Highest-Priority match
Deselected
Read Comparand register
Read Mask Register 1
Read Mask Register 2
Read Memory Array at address
Read Memory Array at Highest-Priority match
Deselected
Deselected
Notes
1
2
2
2
2
2
9
3
3
4
3
3
3
3
3, 10
9
5, 8
6, 8
6, 8
6, 8
6, 8
6, 8
9
5, 8
7, 8
7, 8
7, 8
7, 8
9
Notes:
1. Default Command Write cycle destination (does not require a TCO instruction).
2. To load a value into a register using a TCO instruction takes one Command Write cycle with the “f” bit equal to 1, and
the value to be loaded into the selected register placed in DQ15–0.
3. Reading the contents of a register using a TCO instruction takes two cycles. The first cycle is a Command Write of a
TCO instruction with the “f” bit equal to 0. If the next cycle is a Command Read, the value stored in the selected register
will be read out on the DQ15–0 lines. Additionally, bits 31–16 of the Status register will be read out on the DQ31–16 lines,
except in the case of a Page Address read where 0s will be read on DQ31–16 instead.
4. Default Command Read cycle source (does not require a TCO instruction).
5. Default persistent source and destination after Reset. If other resources were sources or destinations, SPD CR or SPS
CR restores the Comparand register as the destination or source.
6. Selected by executing a Select Persistent Destination instruction.
7. Selected by executing a Select Persistent Source instruction.
8. Access is performed in one or two 32-bit Read or Write cycles. The Segment Control register is used to control the
selection of the desired 32-bit segement(s) by establishing the Segment counters’ limits and start values.
9. Device is deselected if Device Select register setting does not equal Page Address register setting, unless the Device
Select register is set to FFFFH which allows only write access to the device, except in the case of a match. (Writes to
the Device Select register are always active.) Device may also be deselected under locked daisy chain conditions as
shown in Tables 6a and 6b.
10. A Command Read cycle after a TCO PS or TCO PD reads back the Instruction decoder bits that were last set to select a
persistant source or destination. The TCO PS instruction will also read back the Device ID.
Table 4: Input/Output Operations
Rev. 2
8
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