KB2511B 查看數據表（PDF） - Samsung

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KB2511B

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Samsung 

KB2511B

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Hlock

00

0, on

[1], no

[ ] initlal value

Vlock

0, on

[1], no

OPERATING DESCRIPTION

READ MODE

Xray

1,on

[0],off

Polarity detection

H/V pol

V pol

[1],negative [1], negative

Synchro detection

Vext det H/V det

V det

[0],no det [0],no det [0], nodet

GENERAL CONSIDERATIONS

Power Supply

The typical values of the power supply voltages Vcc and VDD are respectively 12V and 5V. Perfect operation is

obtained if Vcc and VDD are maintened in the limits: 10.8 to 13.2V and 4.5 to 5.5V.

In order to avoid erratic operation of the circuit during transient phase of Vcc switching on, or switching off, the

value of Vcc is monitored and the outputs of the circuit are inhibited if Vcc is less than 7.5V typically.

In the same manner, VDD is monitored and internal set-up is made until VDD reaches 4V (see I2C control table for

power on reset).

In order to have a very good power supply rejection, the circuit is internally powered by several internal voltage

references (the unigue typical value of which is 8V). Two of these voltage references are externally accessible, one

for the vertical part and on one for the horizontal one. If needed, these voltage references can be used (until Iload

is less than 5mA). Furthermore it is necessary to filter the a.m. voltage references by the use of external capacitor

connected to ground, in order to minimize the noise and consequently the “jitter” on vertical and horizontal output

signals.

I2C Control

KB2511 belongs to the I2C controlled device family, instead of being controlled by DC voltage on dedicated control

pins, each adjustment can be realized through the I2C interface. The I2C bus is a serial bus with a clock and a data

input. The general function and the bus protocol are specified in the philips-bus data sheets.

The interface (data and clock) is TTL-level compatible. The internal threshold level of the input comparator is 2.2V

(when VDD is 5V). Spikes of up to 500ns are filtered by an integrator and maximum clock speed is limited to

400kHz.

The data line (SDA) can be used in a bidirectional way that means in read-mode the IC clocks out a reply informa-

tion (1byte) to the micro-processor.

The bus protocol prescribes always a full-byte transmission. The first byte after the start condition is used to trans-

mit the IC-address (hexa 8C for write, 8D for read).

Write Mode

In write mode the second byte sent contains the subaddress of the selected function to adjust (or controls to affect)

and the third byte the corresponding data byte. It is possible to send more than one data byte to the IC. If after the

third byte no stop or start condition is detected, the circuit increments automatically the momentary subaddress in

the subaddress counter by one (auto-increment mode). So it is possible to transmit immediately the next data

bytes without sending the IC address or subaddress. It can be useful so as to reinitialize the whole controls very

quickly (flash manner). This procedure can be finished by a stop condition.

The circuit has 16 adjustment capabilities: 3 for horizontal part, 4 for vertical one, 2 for E/W correction, 2 for the

dynamic horizontal phase control, 1 for moire option, 3 for horizontal and vertical dynamic focus and 1 for B+

reference adjustment.

17 bits are also dedicated to several controls (ON/OFF, horizontal forced frequency, sync priority, detection

refresh and Xray reset).

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