KB2511B 查看數據表（PDF） - Samsung

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KB2511B

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

Samsung 

DEFLECTION PROCESSOR FOR MULTISYNC MONITORS

KB2511B

PLL1F

7

1.8KΩ

4.7uF

1uF

Figure 8.

PLL1 is internally inhibited during extracted vertical sync (if any) to avoid taking in account missing pulses or wrong

pulse on phase comparator. The inhibition results from the opening of a switch located between the charge pump

and the filter (see figure 9 ).

The VCO uses an external RC network. It delivers a linear sawtooth obtained by charge and discharge of the

capacitor, by a current proportionnal to the current in the resistor. Typical thresholds of sawtooth are 1.6V and

6.4V.

HSYNC

H-LOCKCAP

8

INPUT

INTERFACE

TRAMEXT

LOCKDET

COMP1

E2

High

Low

LOCK/UNLOCK

STATUS

PLL1F R0 C0

789

I2C

SMFE

TRAMEXT MODE

CHARGE

PLL

PUMP INHIBITION

PHASE

ADJUST

VCO

I2C

HPOS

OSC

Adj.

Figure 9. Block Diagram

25

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