KL5KUSB101 查看數據表（PDF） - Unspecified

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KL5KUSB101

USB to Ethernet Controller

Unspecified 

KL5KUSB101

3. PHY Interface

USB to Ethernet Controller

USB to Ethernet exchanges the serial bit data and messages to the external PHY chip.

3.1 U2E to PHY transmit

Figure 3.1.1 USB to Ethernet to PHY Transmit AC Timing

PHYTCLK

(IN)

PHYTEN

(OUT)

PHYTXD

(OUT)

Ttck

Ttch

Ttcl

Tden1

Tdtd1

first

Tden2

Tdtd2

last

98.09.02 updated

Table 3.1.1 PHY Transmit AC Characteristics (over recommended range)

Symbol

Parameter

Min Typ Max Unit Not

e

Ttck

PHYTCLK period

– 100 – ns 1

Ftck

PHYTCLK frequency

–

10

– MH 1

z

Ttch

PHYTCLK high width

–

50

–

ns –

Ttcl

PHYTCLK low width

–

50

– ns –

Tden1 PHYTEN assert delay

from PHYTCLK rise

–

–

30 ns 2

Tden2 PHYTEN negate delay

from PHYTCLK fall

0

–

– ns 2

Tdtd1 PHYTXD valid delay

from PHYTCLK rise

–

–

28 ns 2

Tdtd2 PHYTEN valid delay

from PHYTCLK fall

0

–

– ns 2

Note: 1) PHY generates the 10MHz clock.

2) 30pF capacitor external load is assumed.

Figure 3.1.2 PHY SQE function AC Timing at Transmit

PHYTEN

(OUT)

PHYCOL

(IN)

Tcol

Tpco

Ver. 2.4

Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com

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