KM681001A 查看數據表（PDF） - Samsung
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KM681001A Datasheet PDF : 9 Pages
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PRELIMINARY
KM681001A
TIMING WAVEFORM OF WRITE CYCLE(4) (CS2 = Controlled)
CMOS SRAM
Address
CS1
CS2
WE
Data in
Data out
tAS(4)
tWC
tAW
tCW(3)
tWP(2)
tWR(5)
High-Z
tLZ
tWHZ(6)
tDW
tDH
Data Valid
High-Z
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition CS1 going low,a
CS2 going high and WE going low ; A write ends at the earliest transition CS1 going high, CS2 going low or WE going high.
tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of CS1 going low or CS2 going high to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high. tWR2
applied in case a write ends as CS2 going low.
6. If OE, CS1, CS2 and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite
phase of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS1 goes low and CS2 goes high simultaneously with WE going or after WE going low, the outputs remain high impedance
state.
9. Dout is the read data of the new address.
10. When CS1 is low and CS2 is high : I/O pins are in the output state. The input signals in the opposite phase leading to the out-
put should not be applied.
FUNCTIONAL DESCRIPTION
CS1
CS2
WE
OE
H
X
X
X*
X
L
X
X
L
H
H
H
L
H
H
L
L
H
L
X
* NOTE : X means Don′t Care.
Mode
Not Select
Not Select
Output Disable
Read
Write
I/O Pin
High-Z
High-Z
High-Z
DOUT
DIN
Supply Current
ISB, ISB1
ISB, ISB1
ICC
ICC
ICC
-8-
Rev 5.0
February 1998
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