KM681001B 查看數據表（PDF） - Samsung

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KM681001B

128K x 8 Bit High-Speed CMOS Static RAM

Samsung 

PRELIMINARY

KM681001B

CMOS SRAM

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS1

CS2

OE

Data out

VCC

ICC

Current

ISB

tRC

tAA

tCO

tOE

tOLZ

tLZ(4,5)

tPU

50%

tHZ(3,4,5)

Valid Data

tOHZ

tOH

tPD

50%

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or

VOL levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to

device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS1=VIL and CS2=VIH.

7. Address valid prior to coincident with CS1 transition low and CS2 transition high.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)

Address

OE

CS1

tWC

tAW

tCW(3)

tWR(5)

CS2

WE

Data in

Data out

tAS(4)

High-Z

tOHZ(6)

tWP(2)

tDW

tDH

Valid Data

High-Z(8)

-6-

Rev 2.0

February 1998

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