KM718FV4021H-5 查看數據表（PDF） - Samsung
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KM718FV4021H-5 Datasheet PDF : 12 Pages
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KM736FV4021
KM718FV4021
128Kx36 & 256Kx18 SRAM
JTAG DC OPERATING CONDITIONS
Parameter
Power Supply Voltage
Input High Level
Input Low Level
Output High Voltage(IOH=-2mA)
Output Low Voltage(IOL=2mA)
Symbol
VDD
VIH
VIL
VOH
VOL
Min
3.15
2.0
-0.3
2.4
VSS
NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification.
JTAG AC TEST CONDITIONS
Parameter
Input High/Low Level
Input Rise/Fall Time
Input and Output Timing Reference Level
NOTE : 1. See SRAM AC test output load on page 5.
Symbol
VIH/VIL
TR/TF
Typ
Max
Unit
3.3
3.45
V
-
VDD+0.3
V
-
0.8
V
-
VDD
V
-
0.4
V
Min
Unit
3.0/0.0
V
2.0/2.0
ns
1.5
V
Note
Note
1
JTAG AC Characteristics
Parameter
TCK Cycle Time
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
Symbol
tCHCH
tCHCL
tCLCH
tMVCH
tCHMX
tDVCH
tCHDX
tSVCH
tCHSX
tCLQV
Min
50
20
20
5
5
5
5
5
5
0
Max
-
-
-
-
-
-
-
-
-
10
Unit
Note
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
JTAG TIMING DIAGRAM
TCK
TMS
TDI
TDO
tCHCH
tMVCH
tDVCH
tCHMX
tCHCL
tCHDX
tCLQV
tCLCH
- 11
Rev 1.0
Dec. 1998
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