KM718FV4021H-5 查看數據表（PDF） - Samsung
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KM718FV4021H-5 Datasheet PDF : 12 Pages
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KM736FV4021
KM718FV4021
128Kx36 & 256Kx18 SRAM
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
FEATURES
• 128Kx36 or 256Kx18 Organizations.
• 3.3V Core Power Supply.
• LVTTL Input and Output Levels.
• Differential, PECL Clock Inputs K, K.
• Synchronous Read and Write Operation
• Registered Input and Registered Output
• Internal Pipeline Latches to Support Late Write.
• Byte Write Capability(four byte write selects, one for each 9bits)
• Synchronous or Asynchronous Output Enable.
• Power Down Mode via ZZ Signal.
• JTAG 1149.1 Compatible Test Access port.
• 119(7x17)Pin Ball Grid Array Package(14mmx22mm)
Organization
Part Number
128Kx36
256Kx18
KM736FV4021H-5
KM736FV4021H-6
KM736FV4021H-7
KM718FV4021H-5
KM718FV4021H-6
KM718FV4021H-7
Cycle
Time
5
6
7
5
6
7
Access
Time
2.5
3.0
3.5
2.5
3.0
3.5
FUNCTIONAL BLOCK DIAGRAM
SA[0:16] or SA[0:17]
CK
SS
SW
SWx
(x=a, b, c, d)
or (x=a, b)
Latch
Latch
SW
Register
SWx
Register
SS
Register
Read
Address
Register
SW
Register
SWx
Register
SS
Register
1
Write
Address
0
Register
G
ZZ
K
CK
K
128Kx36
or
256Kx18
Array
Column Decoder
Write/Read Circuit
01
Data In
Register
Data Out
Register
DQx[1:9]
(x=a, b, c, d)
or (x=a, b)
PIN DESCRIPTION
Pin Name
K, K
SAn
DQn
SW
SWa
SWb
SWc
SWd
ZZ
VDD
Pin Description
Differential Clocks
Synchronous Address Input
Bi-directional Data Bus
Synchronous Global Write Enable
Synchronous Byte a Write Enable
Synchronous Byte b Write Enable
Synchronous Byte c Write Enable
Synchronous Byte d Write Enable
Asynchronous Power Down
Core Power Supply
Pin Name
VDDQ
M1, M2
G
SS
TCK
TMS
TDI
TDO
VSS
NC
Pin Description
Output Power Supply
Read Protocol Mode Pins ( M1=VSS, M2=VDD )
Asynchronous Output Enable
Synchronous Select
JTAG Test Clock
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Data Output
GND
No Connection
-2-
Rev 1.0
Dec. 1998
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