KM718V887 查看數據表（PDF） - Samsung
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KM718V887 Datasheet PDF : 16 Pages
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KM718V887
256Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Input Leakage Current(except ZZ)
IIL VDD=Max ; VIN=VSS to VDD
-2
Output Leakage Current
IOL Output Disabled, VOUT=VSS to VDDQ
-2
Operating Current
Device Selected, IOUT=0mA,
ICC ZZ≤VIL, All Inputs=VIL or VIH
Cycle Time ≥ tCYC Min
-7
-
-8
-
-9
-
Device deselected, IOUT=0mA,
-7
-
ISB ZZ≤VIL, f=Max,
-8
-
All Inputs≤0.2V or ≥ VDD-0.2V
-9
-
Standby Current
ISB1
Device deselected, IOUT=0mA, ZZ≤0.2V,
f=0, All Inputs=fixed (VDD-0.2V or 0.2V)
-
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
Device deselected, IOUT=0mA,
ISB2 ZZ≥VDD-0.2V, f=Max,
All Inputs≤VIL or ≥VIH
VOL IOL = 8.0mA
VOH IOH = -4.0mA
VOL IOL = 1.0mA
VOH IOH = -1.0mA
VIL
VIH
VIL
VIH
-
-
2.4
-
2.0
-0.5*
2.0
-0.3*
1.7
* VIL(Min)=-2.0(Pulse Width ≤ tCYC/2)
** VIH(Max)=4.6(Pulse Width ≤ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V
MAX
2
2
350
325
300
100
90
80
30
UNIT
µA
µA
mA
mA
mA
30
mA
0.4
V
-
V
0.4
V
-
V
0.8
V
VDD+0.5**
V
0.7
V
VDD+0.5**
V
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)
PARAMETER
VALUE
Input Pulse Level(for 3.3V I/O)
0 to 3V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
2ns
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
2ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
VDDQ/2
Output Load
See Fig. 1
-7-
December 1998
Rev. 2.0
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