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KM718V987 查看數據表(PDF) - Samsung

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KM718V987 Datasheet PDF : 21 Pages
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KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0°C to +70°C)
Parameter
Input Leakage Current(except ZZ)
Output Leakage Current
Operating Current
Standby Current
Output Low Voltage(3.3V I/O)
Output High Voltage(3.3V I/O)
Output Low Voltage(2.5V I/O)
Output High Voltage(2.5V I/O)
Input Low Voltage(3.3V I/O)
Input High Voltage(3.3V I/O)
Input Low Voltage(2.5V I/O)
Input High Voltage(2.5V I/O)
Symbol
Test Conditions
IIL VDD=Max ; VIN=VSS to VDD
IOL Output Disabled, Vout=VSS to VDDQ
-7
Device Selected, IOUT=0mA,
-8
ICC
ZZVIL , Cycle Time tCYC Min
-9
-10
-7
Device deselected, IOUT=0mA,
-8
ISB ZZVIL, f=Max, All Inputs0.2V or
-9
VDD-0.2V
-10
Device deselected, IOUT=0mA, ZZ0.2V, f=0,
ISB1
All Inputs=fixed (VDD-0.2V or 0.2V)
Device deselected, IOUT=0mA, ZZVDD-0.2V,
ISB2 f=Max, All InputsVIL or VIH
VOL IOL=8.0mA
VOH IOH=-4.0mA
VOL IOL=1.0mA
VOH IOH=-1.0mA
VIL
VIH
VIL
VIH
Min
-2
-2
-
-
-
-
-
-
-
-
-
-
-
2.4
-
2.0
-0.3*
2.0
-0.3*
1.7
Max
+2
+2
350
330
300
260
140
130
120
120
30
30
0.4
-
0.4
-
0.8
VDD+0.5**
0.7
VDD+0.5**
Unit
µA
µA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing.
2. Data states are all zero.
3. In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
Notes
1,2
3
3
VIH
VSS
VSS-1.0V
20% tCYC(MIN)
TEST CONDITIONS
(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C)
PARAMETER
VALUE
Input Pulse Level(for 3.3V I/O)
0 to 3.0V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O)
1.0V/ns
Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O)
1.0V/ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
VDDQ/2
Output Load
See Fig. 1
- 10 -
May 1999
Rev 4.0

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