KM718V987 查看數據表（PDF） - Samsung
零件编号
产品描述 (功能)
生产厂家
KM718V987 Datasheet PDF : 21 Pages
| |||
KM736V887
KM718V987
256Kx36 & 512Kx18 Synchronous SRAM
256Kx36 & 512Kx18-Bit Synchronous Burst SRAM
FEATURES
• Synchronous Operation.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a lin-
ear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention only for TQFP.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package)
FAST ACCESS TIMES
PARAMETER
Symbol -7 -8 -9 -10 Unit
Cycle Time
tCYC 8.5 10 12 12 ns
Clock Access Time
tCD 7.5 8.5 9.0 10.0 ns
Output Enable Access Time tOE 3.5 3.5 3.5 3.5 ns
GENERAL DESCRIPTION
The KM736V887 and KM718V987 are 9,437,184-bit Synchro-
nous Static Random Access Memory designed for high perfor-
mance second level cache of Pentium and Power PC based
System.
It is organized as 256K(512K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high performance
cache RAM applications; GW, BW, LBO, ZZ. Write cycles are
internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM736V887 and KM718V987 are fabricated using SAM-
SUNG′s high performance CMOS technology and is available
in a 100pin TQFP and 119BGA package. Multiple power and
ground pins are utilized to minimize ground bounce.
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS A′0~A′1
COUNTER
256Kx36 , 512Kx18
MEMORY
ARRAY
ADSP
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
A0~A17
or A0~A18
A0~A1
ADDRESS
REGISTER
A2~A17
or A2~A18
DATA-IN
REGISTER
CONTROL
LOGIC
OUTPUT
BUFFER
OE
ZZ
DQa0 ~ DQd7 or DQa0 ~ DQb7
DQPa ~ DQPd DQPa,DQPb
-2-
May 1999
Rev 4.0
Share Link: 