KS9286 查看數據表（PDF） - Samsung
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KS9286 Datasheet PDF : 35 Pages
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KS9286B/KS9286B-L
PIN DESCRIPTION
DIGITAL SIGNAL PROCESSOR for CDP
PIN NO SYMBOL IO
DESCRIPTION
1
AVDD1
-
Analog VCC1
2
DPDO
O
Charge pump output for Digital PLL
3
DPFIN
I
Filter input for Digital PLL
4
DPFOUT
O
Filter output for Digital PLL
5
CNTVOL
I
VCO control voltage for Digital PLL
6
AVSS1
-
Analog Ground1
7
DATX
O
Digital Audio output data
8
XIN
I
X'tal oscillator input
9
XOUT
O
X'tal oscillator output
10
WDCHO
O
Word clock output of 48bit/Slot (88.2KHz)
11
LRCHO
O
Channel clock output of 48 bit/Slot (44.1KHz)
12
ADATAO
O
Serial audio data output of 48 bit/Slot (MSB first)
13
DVSS1
-
Digital Ground1
14
BCKO
O
Audio data bit clock output of 48 bit/Slot (2.1168MHz)
15
C2PO
O
C2 Pointer for output audio data
16
VREFL2
I
Input terminal2 of reference voltage "L" (Floating)
17
VREFL1
I
Input terminal1 of reference voltage "L" (GND connection)
18
AVDD2
-
Analog VCC2
19
RCHOUT
O
Right-Channel audio output through D/A converter
20
LCHOUT
O
Left-Channel audio output through D/A converter
21
AVSS2
-
Analog ground2
22
VREFH1
I
Input terminal1 of reference voltage "H" (VDD connection)
23
VREFH2
I
Input terminal2 of reference voltage "H" (Floating)
24
EMPH
O
H: Emphasis ON, L: Emphasis OFF
25
LKFS
O
The Lock Status output of frame sync
26
S0S1
O
Output of subcode sync signal(S0+S1)
27
RESET
I
System reset at "L"
28
/ESP
I
ESP function ON/OFF control ("L": ESP function ON, "H": ESP function OFF)
29
SQCK
I
Clock for output Subcode-Q data
4
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