KS9286 查看數據表（PDF） - Samsung

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KS9286

DIGITAL SIGNAL PROCESSOR for CDP

Samsung 

KS9286B/KS9286B-L

DIGITAL SIGNAL PROCESSOR for CDP

PIN DESCRIPTION (continued)

PIN NO SYMBOL IO

DESCRIPTION

30

SQDT

O

Serial output of Subcode-Q data

31

SQOK

O

The CRC (Cycle Redundancy Check) check result signal output of Subcode-Q

32

SBCK

I

Clock for output subcode data

33

SDAT

O

Subcode serial data output

34

DVDD1

-

Digital VDD1

35

MUTE

I

Mute control input ("H": Mute ON)

36

MLT

I

Latch Signal Input from Micom (Schmit Trigger)

37

MDAT

I

Serial data input from Micom (Schmit Trigger)

38

MCK

I

Serial clock input from Micom (Schmit Trigger)

39

RD7

I/O SRAM data I/O port 8 (MSB)

40

RD6

I/O SRAM data I/O port 7

41

RD5

I/O SRAM data I/O port 6

42

RD4

I/O SRAM data I/O port 5

43

RD3

I/O SRAM data I/O port 4

44

RD2

I/O SRAM data I/O port 3

45

RD1

I/O SRAM data I/O port 2

46

RD0

I/O SRAM data I/O port 1 (LSB)

47

FLAG1

I/O Monitoring output for error correction (RA0)

48

FLAG2

I/O Monitoring output for error correction (RA1)

49

FLAG3

I/O Monitoring output for error correction (RA2)

50

FLAG4

I/O Monitoring output for error correction (RA3)

51

FLAG5

I/O Monitoring output for error correction (RA4)

52

/PBCK

I/O Output of VCO/2 (4.3218MHz) (RA5)

53

DVSS2

I/O Digital ground 2

54

FSDW

I/O Window or unprotected frame sync (RA6)

55

ULKFS

I/O Frame sync protection state (RA7)

56

/JIT

I/O Display of either RAM overflow or underflow for + 4 frame jitter margin (RA8)

57

C4M

I/O Only monitoring signal (4.2336MHz) (RA9)

58

C16M

I/O 16.9344MHz signal output(RA10)

59

/WE

I/O Terminal for test

60

/CS

I/O Terminal for test

5

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