74F1763 查看數據表（PDF） - Philips Electronics

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74F1763

Intelligent DRAM controller (IDC)

Philips Electronics 

Philips Semiconductors

Intelligent DRAM controller (IDC)

Product specification

74F1763

TIMING DIAGRAMS (Continued)

CP

REQ ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇNOTEÇÇÇ1 ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ

GNT

RCAA0A0–L–9E9ÇÇ, ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇNNOOTTEEÇÇÇÇÇ23 ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ

PRECHRG = 1 PRECHRG = 0

MA0–9

RAS

NOTE 4

36

REFRESH

ADDR.

33

34

35

REFRESH

ADDR.

33

34

20

NEXT REFRESH ADDRESS

20

CAS

PRECHRG = 1

PRECHRG = 0

PRECHRG = 1

PRECHRG = 0

DTACK

3-STATE

NOTE 1: REQ input is a don’t care during a memory refresh cycle. If REQ is asserted during a refresh cycle, it will be recognized at the first rising CP clock edge, following the refresh

cycle and its associated RAS precharge time (see Figure 4).

NOTE 2: RA0–9 and CA0–9 address inputs may be latched at anytime during a memory refresh cycle. However, a memory access cycle will not begin until after the completion of the

refresh cycle.

NOTE 3: RA0–9 and CA0–9 if in the transparent mode do not propogate to the MA0–9 outputs during a refresh cycle.

NOTE 4: MA0–9 output will contain the present row address on the RA0–RA9 inputs or the last row address latched into the device.

SF01405

Figure 3. Refresh cycle timing following a memory access cycle

1999 Jan 08

10

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