74F1763 查看數據表（PDF） - Philips Electronics

零件编号

产品描述 (功能)

生产厂家

74F1763

Intelligent DRAM controller (IDC)

Philips Electronics 

Philips Semiconductors

Intelligent DRAM controller (IDC)

Product specification

74F1763

PIN DESCRIPTION

SYMBOL

PINS

DIP

REQ

48

GNT

1

PAGE

47

HLDROW

2

PRECHRG

CP

RCP

DTACK

RA0–9

CA0–9

3

46

45

6

44, 42, 40,

35, 33, 31,

29, 27, 25,

23

43, 41, 39,

34, 32, 30,

28, 26, 24,

22

RAS

4

CAS

MA0–9

ALE

VCC

GND

5

7–10,

15–20

21

36–38

11–14

TYPE

NAME AND FUNCTION

Input

Output

Input

Input

Input

Input

Input

Output

Active Low Memory Access Request input, must be asserted for the entire DRAM access cycle.

REQ is sampled on the rising edge of the CP clock.

Active High Grant output. When High indicates that a DRAM access (inactive during refresh)

cycle has begun. Asserted from the rising edge of the CP clock.

Active Low Page-Mode Access input. Forces the IDC to keep RAS asserted for as long as the

PAGE input is Low and REQ is asserted Low.

Row Address Hold input. If Low will configure the IDC to maintain the row addresses for a full

CP clock cycle after RAS is asserted. If High will program the IDC to maintain row addresses for

a 1/2 CP clock cycle after RAS is asserted.

RAS Precharge input. A Low will program the IDC to guarantee a minimum of 4 CP clock cycles

of precharge. A High will guarantee 3 clock cycles of precharge.

Clock input. Used by the Controller for all timing and arbitration functions.

Refresh Clock input. Divided internally by 64 to produce an internal Refresh Request.

Active Low, 3-state Data Transfer Acknowledge output. Enabled by the REQ input and asserted

four clock cycles after the assertion of RAS, 3-stated when REQ goes High.

Inputs Row Address inputs.

Inputs

Column Address inputs. Propagated to the MA0–9 outputs 1 CP clock cycle after RAS is

asserted, if HLDROW = 0 or 1/2 clock cycle later if HLDROW is 1.

Output

Output

Output

Input

Active Low Row Address Strobe. Asserted for four clock cycles during each refresh cycle

regardless of the PAGE input. Also asserted for four clock cycles during processor access if the

PAGE input is High. If PAGE is Low, RAS is negated upon negation of PAGE or REQ, whichever

occurs first.

Active Low Column Address Strobe. Always asserted 1.5 CP clock cycles after the assertion of

RAS. Negated upon negation of REQ. HLDROW input pin does not affect RAS to CAS timing.

DRAM multiplexed address outputs. Row and column addresses asserted on these pins during

an access cycle. Refresh counter addresses presented on these outputs during refresh cycles.

Active Low Address Latch Enable input. A Low on this pin will cause the address latches to be

transparent. A High level will latch the RA0–9 and CA0–9 inputs.

+5V "10% Supply voltage.

Ground

1999 Jan 08

4

Share Link: