KS8721BL 查看數據表（PDF） - Micrel
零件编号
产品描述 (功能)
生产厂家
KS8721BL Datasheet PDF : 35 Pages
| |||
Micrel, Inc.
KS8721BL/SL
Pin Description
Pin Number
1
Pin Name
MDIO
2
MDC
3
RXD3/
PHYAD
4
RXD2/
PHYAD2
5
RXD1/
PHYAD3
6
RXD0/
PHYAD4
7
VDDIO
8
GND
9
RXDV/
CRSDV/
PCS_LPBK
10
RXC
11
RXER/ISO
12
GND
13
VDDC
14
TXER
15
TXC/
REFCLK
16
TXEN
17
TXD0
18
TXD1
19
TXD2
20
TXD3
21
COL/
RMII
22
CRS/
RMII_BTB
23
GND
Type(1)
I/O
I
Ipd/O
Ipd/O
Ipd/O
Ipd/O
P
Gnd
Ipd/O
O
Ipd/O
Gnd
P
Ipd
I/O
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd/O
Ipd/O
Gnd
Pin Function
Management Independent Interface (MII) Data I/O. This pin requires an external 4.7K
pull-up resistor.
MII Clock Input. This pin is synchronous to the MDIO.
MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK.
When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII.
RXD [3..0] is invalid when RXDV is de-asserted.
During reset, the pull-up/pull-down value is latched as PHYADDR [1]. See “Strapping
Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[2]. See “Strapping
Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[3]. See “Strapping
Options” section for details.
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHYADDR[4]. See “Strapping
Options” section for details.
Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of voltage regulator. See
“Circuit Design Ref. for Power Supply" section for details.
Ground.
MII Receive Data Valid Output.
During reset, the pull-up/pull-down value is latched as PCS_LPBK. See “Strapping
Options” section for details.
MII Receive Clock Output. Operating at 25MHz = 100Mbps, 2.5MHz = 10Mbps.
MII Receive Error Output.
During reset, the pull-up/pull-down value is latched as ISOLATE during reset. See
“Strapping Options” section for details.
Ground.
Digital core 2.5V only power supply. See “Circuit Design Ref. for Power Supply" section
for details.
MII Transmit Error Input.
MII Transmit Clock Output.
Input for crystal or an external 50MHz clock. When REFCLK pin is used for REF clock
interface, pull up XI to VDDPLL 2.5V via 10kΩ resistor and leave XO pin unconnected.
MII Transmit Enable Input.
MII Transmit Data Input.
MII Transmit Data Input.
MII Transmit Data Input.
MII Transmit Data Input.
MII Collision Detect Output.
During reset, the pull-up/pull-down value is latched as RMII select. See “Strapping
Options” section for details.
MII Carrier Sense Output.
During reset, the pull-up/pull-down value is latched as RMII back-to-back mode when
RMII mode is selected. See “Strapping Options” section for details.
Ground.
June 2009
7
M9999-062509-1.3
Share Link: 