KSZ8051MLL 查看數據表（PDF） - Micrel

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KSZ8051MLL

10Base-T/100Base-TX Physical Layer Transceiver

Micrel 

Micrel, Inc.

KSZ8051MLL

List of Figures

Figure 1. Auto-Negotiation Flow Chart........................................................................................................................... 16

Figure 2. KSZ8051MLL MII Interface............................................................................................................................. 18

Figure 3. KSZ8051MLL and KSZ8041FTL Back-to-Back Media Converter .................................................................. 19

Figure 4. Typical Straight Cable Connection ................................................................................................................. 21

Figure 5. Typical Crossover Cable Connection ............................................................................................................. 22

Figure 6. KSZ8051MLL Power and Ground Connections ............................................................................................. 26

Figure 7. MII SQE Timing (10Base-T) ........................................................................................................................... 39

Figure 8. MII Transmit Timing (10Base-T) ..................................................................................................................... 40

Figure 9. MII Receive Timing (10Base-T) ...................................................................................................................... 41

Figure 10. MII Transmit Timing (100Base-TX)............................................................................................................... 42

Figure 11. MII Receive Timing (100Base-TX)................................................................................................................ 43

Figure 12. Auto-Negotiation Fast Link Pulse (FLP) Timing ........................................................................................... 44

Figure 13. MDC/MDIO Timing........................................................................................................................................ 45

Figure 14. Reset Timing................................................................................................................................................. 46

Figure 15. Recommended Reset Circuit........................................................................................................................ 47

Figure 16. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output................................................ 47

Figure 17. Reference Circuits for LED Strapping Pins................................................................................................... 48

Figure 18. 25MHz Crystal / Oscillator Reference Clock Connection ............................................................................. 50

July 2010

6

M9999-071210-1.0

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