AS6UA25617 查看數據表（PDF） - Alliance Semiconductor
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产品描述 (功能)
生产厂家
AS6UA25617
Alliance Semiconductor
AS6UA25617 Datasheet PDF : 9 Pages
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Preliminary information
June 2000
AS6UA25617
1.65V to 3.6V 256K×16 Intelliwatt™ low power CMOS SRAM with two chip enables
Features
• AS6UA25617
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 262,144 words × 16 bits
• 2.7V to 3.6V at 55 ns
• 2.3V to 2.7V at 70 ns
• 1.65V to 2.3V at 100 ns
• CS1 and CS2 for chip selection
• Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
- 68 mW at 2.7V and 70 ns
- 28 mW at 2.3 V and 100 ns
• Low power consumption: STANDBY
- 72 µW max at 3.6V
- 41 µW max at 2.7V
- 28 µW max at 2.3V
• 1.2V data retention
• Equal access and cycle times
• Easy memory expansion with CS1, CS2, OE inputs
• Smallest footprint package
- 400-mil 44-pin TSOP II
- 48-ball FBGA
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
I/O
buffer
WE
UB
OE
LB
CS1
CS2
Selection guide
Min
Product
(V)
AS6UA25617
2.7
AS6UA25617
2.3
AS6UA25617*
1.65
1024 × 256 × 16
Array
(4,194,304)
Control circuit
Column decoder
VCC Range
Typ2
(V)
3.0
2.5
2.0
VDD
VSS
Max
(V)
3.6
2.7
2.3
Pin arrangement (top view)
400-pin 400-mil TSOP II
A0
A1
A2
A3
A4
CS1
I/O1
I/O2
I/O3
I/O4
I/VVOCS5CS
I/O6
I/O7
I/O8
WE
A5
A6
A7
A8
A9
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 36
10 35
11 34
12 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
VVI/CSOSC12
I/O11
I/O10
I/O9
CS2
A14
A13
A12
A11
A10
48-CSP Ball-Grid-Array Package
123456
A LB OE A0 A1 A2 CS2
B I/O9 UB A3 A4 CS1 I/O1
C I/O10 I/O11 A5 A6 I/O2 I/O3
D VSS I/O12 A17 A7 I/O4 VCC
E VCC I/O13 NC A16 I/O5 VSS
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 WE I/O8
H NC A8 A9 A10 A11 NC
Speed
(ns)
55
70
100
Power Dissipation
Operating (ICC1)
Max (mA)
Standby (ISB2)
Max (µA)
2
20
1
15
1
12
ALLIANCE SEMICONDUCTOR
1
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