AS6UA25617-TC 查看數據表（PDF） - Alliance Semiconductor
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AS6UA25617-TC
Alliance Semiconductor
AS6UA25617-TC Datasheet PDF : 9 Pages
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AS6UA25617
Functional description
The AS6UA25617 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144
words × 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55/70/100 ns are ideal for low-power applications. Active high and
low chip selects (CS1 and CS2) permit easy memory expansion with multiple-bank memory systems.
When CS1 is high, or UB and LB are high or CS2 is low, the device enters standby mode: the AS6UA25617 is guaranteed not
to exceed 72 µW power consumption at 3.6V and 55 ns; 41 µW at 2.7V and 70 ns; or 28 µW at 2.3V and 100 ns. The device
also returns data when VCC is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS1) low, UB and/or LB low, and CS2 high. Data
on the input pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CS1, CS2 (write cycle 2). To avoid bus
contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write
enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS1) low, UB and/or LB low, with write enable
(WE) and CS2 high. The chip drives I/O pins with the data word referenced by the input address. When either chip select or
output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode.
This device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from either a single 1.65V to 3.6V supply. The device is
available in the JEDEC standard 48-ball FBGA and 44-pin TSOPII packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
Max
Unit
Voltage on VCC relative to VSS
Voltage on any I/O pin relative to GND
Power dissipation
Storage temperature (plastic)
Temperature with VCC applied
DC output current (low)
VtIN
VtI/O
PD
Tstg
Tbias
IOUT
–0.5
VCC + 0.5
V
–0.5
V
–
1.0
W
–65
+150
°C
–55
+125
°C
–
20
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS1 CS2 OE WE LB UB I/O1–8 I/O9–16
Mode
H
X
X
X
X
X
High-Z High-Z
Deselected
X
L
X
X
X
X
High-Z High-Z
Deselected
X
X
X
X
H
H
High-Z
High-Z
Deselected
L
H
H
H
L
X
High-Z High-Z Output Disabled
L
H
H
H
X
L
High-Z High-Z Output Disabled
L
H
L
H
L
H
DOUT
High-Z Lower Byte Read
L
H
L
H
H
L
High-Z
DOUT
Upper Byte Read
L
H
L
H
L
L
DOUT
DOUT
Word Read
L
H
X
L
L
H
DIN
High-Z Lower Byte Write
L
H
X
L
H
L
High-Z
DIN
Upper Byte Write
L
H
X
L
L
L
DIN
DIN
Word Write
Key: X = Don’t care, L = Low, H = High.
Power
Standby
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
2
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