A6UA25617-TI 查看數據表（PDF） - Alliance Semiconductor

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A6UA25617-TI

1.65V to 3.6V 256K×16 Intelliwatt™ low power CMOS SRAM with two chip enables

Alliance Semiconductor 

AS6UA25617

Write cycle (over the operating range)

–55

–70

Parameter

Symbol Min Max Min Max

Write cycle time

tWC

55

–

70

–

Chip selects to write end

tCW

40

–

60

–

Address setup to write end

tAW

40

–

60

–

Address setup time

tAS

0

–

0

–

Write pulse width

tWP

35

–

55

–

Address hold from end of write

tAH

0

–

0

–

Data valid to write end

tDW

25

–

30

–

Data hold time

tDH

0

–

0

–

Write enable to output in high Z tWZ

0

20

0

20

Output active from write end

tOW

5

–

5

–

UB/LB low to end of write

tBW

35

–

55

–

Shaded areas indicate preliminary information.

Write waveform 1 (WE controlled)

tWC

Address

tCW

CS1

–100

Min Max Unit Notes

100

–

ns

80

–

ns

12

80

–

ns

0

–

ns

12

70

–

ns

0

–

ns

40

–

ns

0

–

ns

4, 5

0

20

ns

4, 5

5

–

ns

4, 5

70

–

ns

tAH

CS2

LB, UB

WE

tCW

tBW

tAS

tAW

DIN

DOUT

tWZ

Data undefined

Write waveform 2 (chip selects controlled)

Address

tAS

CS1

CS2

tAS

LB, UB

tWC

tCW

tAW

tAW

tCW

tBW

WE

DIN

DOUT

tCLZ

High Z

tWZ

Data undefined

tAH

tWP

tDW

tDH

Data valid

tOW

High Z

tAH

tAH

tWP

tDW

tDH

Data valid

tOW

High Z

5

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