AS6UA25617-TI 查看數據表（PDF） - Alliance Semiconductor
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AS6UA25617-TI
Alliance Semiconductor
AS6UA25617-TI Datasheet PDF : 9 Pages
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AS6UA25617
Data retention characteristics (over the operating range)
Parameter
Sym
Test conditions
VCC for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
VDR
ICCDR
tCDR
tR
VCC = 1.2V
CS1 ≥ VCC – 0.1V or
UB = LB > VCC – 0.1V
VIN ≥ VCC – 0.1V or
VIN ≤ 0.1V
Data retention waveform
Data retention mode
VCC
VCC
VDR ≥ 1.2V
tCDR
CS1
VIH
VDR
CS2
VIH
VDR
tCDR
AC test loads and waveforms
R1
VCC
OUTPUT
30 pF
R2
INCLUDING
JIG AND
SCOPE
(a)
R1
VCC
OUTPUT
5 pF
R2
INCLUDING
JIG AND
SCOPE
(b)
Min
Max
Unit
1.2V
3.6
V
–
2
mA
0
–
ns
tRC
–
ns
VCC
tR
VIH
VIH
tR
Thevenin equivalent:
RTH
OUTPUT
V
ALL INPUT PULSES
VCC Typ 90%
90%
10%
GND
< 5 ns
10%
(c)
Parameters
3.0V
2.5V
2.0V
R1
1105
16670
15294
R2
1550
15380
11300
RTH
645
8000
6500
VTH
1.75V
1.2V
0.85V
Notes
1 During VCC power-up, a pull-up resistor to VCC on CS1 is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions.
4 tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6 WE is HIGH for read cycle.
7 CS1 and OE are LOW and CS2 is HIGH for read cycle.
8 Address valid prior to or coincident with CS1 transition LOW and CS2 HIGH.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CS1 or WE must be HIGH or CS2 LOW during address transitions. Either CS1 or WE asserting HIGH terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 CE1 and CE2 have identical timing.
13 1.2V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at HIGH Z and LOW Z parameters, where C = 5pF.
Unit
Ohms
Ohms
Ohms
Volts
6
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