SAA7165WP 查看數據表（PDF） - Philips Electronics
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SAA7165WP Datasheet PDF : 28 Pages
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Philips Semiconductors
Video Enhancement and Digital-to-Analog
processor (VEDA2)
Product specification
SAA7165
handbook, full pagewidth
LL27
(LLC)
CREF
internal
bus clock
(LLC2)
HREF
start of
active line
Byte number for pixels:
Y signal
0
1
2
3
4
5
6
7
50 Hz
U and V signal
U0
V0
U2
V2
U4
V4
U6
V6
Y signal
60 Hz
U and V signal
0
1
2
3
4
5
6
7
U0
V0
U2
V2
U4
V4
U6
V6
MEH268
a. Start of active line.
handbook, fullLpLa2g7ewidth
(LLC)
CREF
internal
bus clock
(LLC2)
HREF
Byte number for pixels:
Y signal
50 Hz
U and V signal
714
U714
715
V714
716
U716
717
V716
end of
active line
718
U718
719
V718
Y signal
60 Hz
U and V signal
714
U714
715
V714
716
U716
717
V716
718
U718
719
V718
b. End of active line.
MEH269
Fig.3 Line control by HREF for 4 : 2 : 2 format, CREF = 13.5 MHz; HREF = 720 pixel; 50 and 60 Hz field.
1996 Aug 20
8
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