L6928(2006) 查看數據表（PDF） - STMicroelectronics
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L6928 Datasheet PDF : 16 Pages
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Operation description
L6928
4.3
Slope compensation
In current mode architectures, when the duty cycle of the application is higher than
approximately 50%, a pulse-by-pulse instability (the so called sub harmonic oscillation) can
occur.
To allow loop stability also in these conditions a slope compensation is present. This is
realized by reducing the current flowing through the inductor necessary to trigger the COMP
comparator (with a fixed value for the COMP pin voltage).
With a given duty cycle higher than 50%, the stability problem is particularly present with an
higher input voltage (due to the increased current ripple across the inductor), so the slope
compensation effect increases as the input voltage increases.
From an application point of view, the final effect is that the peak current limit depends both
on the duty cycle (if higher than approximately 40%) and on the input voltage.
4.4
Loop stability
Since the device is realized with a current mode architecture, the loop stability is usually not
a big issue. For most of the application a 220pF connected between the COMP pin and
ground is enough to guarantee the stability. In case very low ESR capacitors are used for
the output filter, such as multilayer ceramic capacitors, the zero introduced by the capacitor
itself can shift at very high frequency and the transient loop response could be affected.
Adding a series resistor to the 220pF capacitor can solve this problem.
The right value for the resistor (in the range of 50K) can be determined by checking the load
transient response of the device. Basically, the output voltage has to be checked at the
scope after the load steps required by the application. In case of stability problems, the
output voltage could oscillates before to reach the regulated value after a load step.
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