LB11691 查看數據表（PDF） - SANYO -> Panasonic
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LB11691
SANYO -> Panasonic
LB11691 Datasheet PDF : 21 Pages
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LB11691
Three-phase logic truth table
(1)120° (HSEL = “L”)
F/R = “L”
F/R = “H”
IN1
IN2
IN3
IN1
IN2
IN3
1
H
L
H
L
H
L
2
H
L
L
L
H
H
3
H
H
L
L
L
H
4
L
H
L
H
L
H
5
L
H
H
H
L
L
6
L
L
H
H
H
L
Upper side gate
VH
WH
WH
UH
UH
VH
Lower side gate
HP
UL
H
UL
L
VL
H
VL
L
WL
H
WL
L
(2)60° (HSEL = “H”)
F/R = “L”
IN1
IN2
IN3
1
H
H
H
2
L
H
H
3
L
L
H
4
L
L
L
5
H
L
L
6
H
H
L
F/R = “H”
IN1
IN2
IN3
L
L
L
H
L
L
H
H
L
H
H
H
L
H
H
L
L
H
Upper side gate
VH
WH
WH
UH
UH
VH
Lower side gate
HP
UL
H
UL
L
VL
H
VL
L
WL
H
WL
L
• The condition with the upper gate = VH and the lower gate = UL corresponds to a state in which the upper FET is
turned ON when the VH pin is connected and the lower FET is turned ON when the UL pin is connected.
• The HP output is an open collector output. Therefore, “H” level corresponds to an open state.
Pin Assignment
WH WOUT WL (NC) RF RFGND GND VB VCC V12 V5 LVS CP1 CP2 HP FAIL CSD RC
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
LB11691
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
VL VOUT VH UL UOUT UH IN1 IN2 IN3 RES HSEL F/R (NC) EI+ EI- TOC PWM FV
Top view
No.A0879-5/21
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