LB1951 查看數據表（PDF） - SANYO -> Panasonic
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LB1951 Datasheet PDF : 9 Pages
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LB1951V
Allowable Operating Ranges at Ta = 25°C
Parameter
Supply voltage
Hall input amplitude
Symbol
VCC1
VCC2
Vs
VHALL
Conditions
Between Hall inputs
Ratings
2.7 to 6.0
3.5 to 9.0
to VCC 2
±20 to ±80
Unit
V
V
V
mV0-p
Electrical Characteristics at Ta = 25°C, VCC1 = 3 V, VCC2 = 4.75 V, VS = 1.5 V
Parameter
[Supply Current]
Symbol
Conditions
Ratings
min typ max Unit
Supply current 1
Supply current 2
Static current 1
Static current 2
VS static current
[VX1]
Upper side residual voltage
Lower side residual voltage
[VX2]
Upper side residual voltage
Lower side residual voltage
Output side saturation voltage
Overlap
[Hall Amplifier]
Hall amplifier input offset voltage
Hall amplifier common-mode
input range
Hall amplifier I/O voltage gain
[Standby Pin]
ICC1
ICC2
ICCQ1
ICCQ2
ISQ
Iout = 100 mA
Iout = 100 mA
VSTBY = 0 V
VSTBY = 0 V
VSTBY = 0 V
VXH1
VXL1
Iout = 0.2 A
Iout = 0.2 A
VXH2
VXL2
Vosat
O.L
Iout = 0.5 A
Iout = 0.5 A
Iout = 0.8 A, Sink + Source
RL =39 Ω × 3, R angle = 20 kΩ
Note 1
VHOFF
VHCM
VGVH
Note 2
R angle = 20 kΩ
R angle = 20 kΩ
3.0 5.0 mA
7.0 10.0 mA
1.5 3.0 mA
100 µA
40 100 µA
0.15 0.22 0.29 V
0.16 0.21 0.26 V
0.25 0.40 V
0.25 0.40 V
1.40 V
70 77 84 %
–5
+5 mV
0.95
2.4 V
24.5 27.5 30.5 dB
Stand-by pin high-level voltage
Standby pin low-level voltage
Standby pin input current
Standby leakage current
[FRC Pin]
FRC pin high-level voltage
FRC pin low-level voltage
FRC pin input current
FRC pin leakage current
[VH]
VSTH
VSTL
ISTIN
ISTLK
VSTBY = 3 V
VSTBY = 0 V
VFRCH
VFRCL
IFRCIN
IFRCLK
VFRC = 3 V
VFRC = 0 V
2.5
V
0.4 V
25 40 µA
–30 µA
2.5
V
0.4 V
20 30 µA
–30 µA
Hall supply voltage
VH (–) pin voltage
[FG Comparator]
Input offset voltage
Input bias current
Input bias current offset
Common-mode input range
Output high-level voltage
Output low-level voltage
Voltage gain
Output current (Sink)
[TSD]
TSD operating temperature
TSD temperature hysteresis width
VHALL
VH(–)
IH = 5 mA, VH (+)–VH (–)
IH = 5 mA
VFGOFF
IbFG
∆IbFG
VFGCM
VFGOH
VFGOL
VGFG
IFGOs
VFGIN+ =VFGIN– = 1.5 V
VFGIN+ =VFGIN– = 1.5 V
At internal pull-up
At internal pull-up
(Design target) Note 2
With output pin ‘‘L’’
T-TSD (Design target value) Note 2
∆TSD (Design target value) Note 2
0.85 0.95 1.05 V
0.81 0.88 0.95 V
–3
+3 mV
500 nA
–100
+100 nA
1.2
2.5 V
2.8
V
0.2 V
100
dB
5 mA
180
°C
20
°C
Note 1: Overlapping specifications are assumed to be test specifications.
Note 2: For parameters which have an entry of (Design target value) in the ‘‘Conditions’’ column, no measurements are made.
No. 5232-2/9
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