LC723483W 查看數據表（PDF） - SANYO -> Panasonic
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LC723483W Datasheet PDF : 15 Pages
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LC723481W/2W/3W
Continued from preceding page.
Pin No.
Pin
I/O
Function
54
BRES
System reset input.
I In CPU operating mode or halt mode, applications must apply a low level for at least
one full machine cycle to reset the system and restart execution with the PC set to
location 0. This pin is connected in parallel with the internal power on reset circuit.
I/O circuit
N-channel open-drain
Tuning voltage generation circuit outputs.
49
TU
O These pins include a n-ch transistor, and a tuning voltage can be generated by
connecting external coil, diode, and capacitor components.
55
HCTR
57
FMIN
58
AMIN
Special-purpose universal counter input port
• To measure a frequency, set up HCTR frequency measurement mode and the
measurement time with a UCS instruction (b3 = 0, b2 = 0) and start the count with
a UCC instruction.
Measurement
UCS b3 b2 Input pin mode
UCS b1 b0
00
Measurement time
1 ms
I
00
Frequency
HCTR measurement
01
4 ms
10
8 ms
01
—
—
11
32 ms
10
—
—
The CNTEND flag is set when the count completes. Since the input circuit functions
as an AC amplifier in this mode, the input must be capacitance coupled.
This pin goes to the input disabled state in backup mode, halt mode, PLL stop mode,
and after a reset.
FM VCO (local oscillator) input.
This pin is selected with the PLL instruction CW1.
CW1 b1, b0
Bandwidth
I
00
10 to 250 MHz
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
AM VCO (local oscillator) input.
This pin and the bandwidth are selected with the PLL instruction CW1.
CW1 b1, b0
Bandwidth
I
10
2 to 40 MHz (SW)
1 1 0.5 to 10 MHz (MW, LW)
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
CMOS amplifier input
CMOS amplifier input
CMOS amplifier input
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No. 7253-9/15
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