LC72714 查看數據表（PDF） - SANYO -> Panasonic
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LC72714 Datasheet PDF : 29 Pages
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LC72714W
Allowable Operating Ranges: Parallel Interface at Ta = –40 to +85°C, VSS = 0 V
Parameter
Address to RD setup
RD to address hold
RD low-level width
RD low-level width (when RDY is used)
RD cycle wait
RDY width (Register read)
RD data hold
Address to WR setup
WR to address hold
WR cycle wait
WR low-level width
WR data hold
RDY output delay
Corrected output RD width
Corrected output RD width
(when RDY is used)
RDY width (corrected output read)
DACK to DREQ delay
DMA cycle wait
RD low-level width (DMA)
Symbol
Conditions
tSARD
tHARD
tWRDL1
tWRDL2
tCYRD
tWRDY
tRDH
tSAWR
tHAWR
tCYWR
tWWRL
tWDH
tDRDY
tWDRD1
tWDRD2
tWDRDY
tDREQ
tCYDM
tWRDM
A0/CL, A1/CE, A2/DI, A3, RD
A0/CL, A1/CE, A2/DI, A3, RD, tWRDL=>250 ns
RD
RD
A0/CL, A1/CE, A2/DI, A3, RD
RDY
RD, DATn
A0/CL, A1/CE, A2/DI, A3, WR
A0/CL, A1/CE, A2/DI, A3, WR
A0/CL, A1/CE, A2/DI, A3, WR
WR
WR, DATn
RD, RDY
RD (BUSWD = L 8 bits)
RD (BUSWD = H 16 bits)
RD (BUSWD = L 8 bits)
RD (BUSWD = H 16 bits)
RDY (BUSWD = L 8 bits)
RDY ((BUSWD = H 16 bits)
DREQ, DACK
RD, DREQ
RD
min
20
–20
280
100
150
60
0
20
20
150
200
0
0
300
540
100
300
60
300
300
Ratings
typ
Unit
max
ns
ns
ns
280
ns
ns
230
ns
ns
ns
ns
ns
ns
ns
50
ns
ns
ns
300
ns
540
ns
230
ns
490
ns
260
ns
420
ns
ns
Notes:
Application designs must take the RDY signal output delay into consideration if the RDY signal is used as the CPU bus wait signal.
When the RDY signal is used, the “RD low-level width” and the “Corrected output RD width” values express the basic timing (excluding the wait
time) settings for the CPU bus.
If the RDY signal is not used, (that is, if no wait states are inserted) the value of the RD low-level width will be 280 ns (minimum).
Electrical Characteristics at VDD = +2.7 to +3.6 V, within the allowable operating ranges
Parameter
High-level output voltage
Low-level output voltage
High-level input current
Low-level input current
Input resistance
Reference supply voltage output
Bandpass filter center frequency
–3 dB bandwidth
Group delay
Gain
Stop band attenuation
Output off leakage current
Hysteresis voltage
Internal feedback resistor
Current drain
Symbol
Conditions
VOH1
VOH2
VOL1
VOL2
VOL3
IIH1
IIH2
IIL
Rmpx
Vref
Fc
Fbw
Dgd
Gain
ATT1
ATT2
ATT3
ATT4
IOFF
VHIS
Rf
IDD
Io = 1 mA, BCK, FCK, BLOCK, FLOCK,
CRC4, CLK16DATA
Io = 2 mA, INT, RDY, DREQ, D0 to D15
Io = 1 mA, Pins for which VOH1 applies
Io = 2 mA, Pins for which VOH2 applies
Io = 1 mA, DO, INT
VIN = 5.5 V, A0/CL, A1/CE, A2/DI, RST,
STNBY
VIN = VDDD, All input pins other than IIH1
VIN = VSSD, All input pins
MPXIN – Vssa f = 100 kHz
Vref, Vdda = 3 V
FLOUT
FLOUT
FLOUT
FLOUT – MPXIN f = 76 kHz
FLOUT f = 50 kHz
FLOUT f = 100 kHz
FLOUT f = 30 kHz
FLOUT f = 150 kHz
V0 = VDDD, DO
A0/CL, A1/CE, A2/DI, A3, CS, RD, WR,
DACK, IOCNT1, IOCNT2, RST, STNBY
XIN, XOUT
min
VDD – 0.4
VDD – 0.4
Ratings
typ
50
1.5
76.0
19.0
–7.5
20
25
15
50
50
0.1 VDDD
1.0
12
Unit
max
V
V
0.4
V
0.4
V
0.4
V
1.0
µA
1.0
µA
–1.0
µA
kΩ
V
kHz
kHz
+7.5
µs
dB
dB
dB
dB
dB
1.0
µA
V
MΩ
20 mA
No. 6871-3/29
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