LC72725NV 查看數據表（PDF） - SANYO -> Panasonic
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LC72725NV Datasheet PDF : 8 Pages
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LC72725M, LC72725V, LC72725NV
Inputs and Outputs
TEST
0
0
1
1
MODE
0
1
0
1
Circuit operating mode
Master mode
Slave mode
Standby mode (crystal oscillator stopped)
IC test mode (Cannot be set by users.)
RDCL pin
Clock output
Clock input
—
—
RDS-ID/READY pin
RDS-ID output
READY output
—
—
RST = 0
RST = 1
RST pin
Normal operation
The RDS-ID and demodulation circuits are cleared, and (in slave mode) the READY state and memory are cleared.
Master mode RDS-ID output (active high)
Slave mode Readout data ready output (active high)
RDS ID/READY pin
Note: The RDS-ID (READY) pin is an n-channel open-drain output, and data is read out by connecting a pull-up resistor.
* LC72723: Active-low
RDCL/RDDA Output Timing
• Master mode
RST Operation
• Master mode
RDCL Control in Slave Mode
Caution: After an RST input, the
RDCL and RDDA outputs
stop at the high level until
the first RDS ID detection.
No. 7672-6/8
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