LC72725M 查看數據表（PDF） - SANYO -> Panasonic
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LC72725M Datasheet PDF : 8 Pages
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LC72725M, LC72725V, LC72725NV
Parameter
RDCL setup time
RDCL high-level time
RDCL low-level time
Data output time
READY output time
Ready high-level time
Symbol
Conditions
tCS RDCL, RDDA
tCH RDCL
tCL
RDCL
tDC RDCL, RDDA
tRC RDCL, READY
tRH READY
min
0
0.75
0.75
Ratings
typ
Unit
max
µs
µs
µs
0.75
µs
0.75
µs
107 ms
Notes:1. Start RDCL clock input after the READY signal goes high. Applications must stand by with RDCL held low when the READY pin is low.
2. Each time the RDCL input is switched from low to high to low, the application must check the READY signal level after the period tRC has elapsed
once RDCL has been set low. If READY is at the high level, the application may apply the next RDCL clock cycle. If READY is low, the application
must stop RDCL input at that point.
3. When the above timing conditions are met, RDDA can be read at either the rise or fall of the RDCL signal.
4. After the last data from memory has been read, READY will be low once the period tRC has elapsed after the fall of the RDCL signal. If even 1 bit of
data has been written to memory, READY will be high and the application will be able to read that data.
5. When switching channels, it is desirable to immediately reset memory and the READY pin with an RST input. If this is not done, data received on
the previous channel may remain in memory. When the IC is reset, data is not written until the RDS-ID is detected, and therefore, the READY
signal will go high after the RDS-ID is detected. (Although the RDS-ID is not output in slave mode, it is detected internally in the IC.) After an RST
input, once an RDS-ID has been detected, all received data will be written to memory regardless of the RDS-ID detection state.
6. The readout mode may be switched between master and slave modes during readout. Applications must observe the following points to assure
data continuity during this operation.
• Data acquisition timing in master mode
Data must be read on the falling edge of RDCL.
• Timing of the switch from master mode to slave mode
After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE high immediately. Then, the
microcontroller starts output by setting the RDCL signal low. The microcontroller RDCL output must start within 840 µs (tms) after RDCL went low.
In this case, if the last data read in master mode was data item n, then data starting with item n+1 will be written to memory.
• Timing of the switch from slave mode to master mode
After all data has been read from memory and READY has gone low, the application must then wait until READY goes high once again the next
time (timing A in the figure), immediately read out one bit of data and input the RDCL clock. Then, at the point READY goes low, the
microcontroller must terminate RDCL output and then set MODE low. The application must switch MODE to low within 840 µs (tms) after READY
goes high (timing A in the figure).
RDCL (microcontroller status)
RDCL (IC status)
No. 7672-7/8
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