LC75824E 查看數據表（PDF） - SANYO -> Panasonic
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LC75824E Datasheet PDF : 17 Pages
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LC75824E, 75824W
Allowable Operating Ranges at Ta = –40 to 85°C, VSS = 0 V
Parameter
Supply voltage
Input voltage
Input high-level voltage
Input low-level voltage
Recommended external
resistance
Recommended external
capacitance
Guaranteed oscillation range
Data setup time
Data hold time
CE wait time
CE setup time
CE hold time
High-level clock pulse width
Low-level clock pulse width
Rise time
Fall time
INH switching time
Symbol
VDD
VDD1
VDD2
VIH
VIL
ROSC
VDD
VDD1
VDD2
CE, CL, DI, INH
CE, CL, DI, INH
OSC
Conditions
COSC
fOSC
tds
tdh
tcp
tcs
tch
tøH
tøL
tr
tf
tc
OSC
OSC
CL, DI: Figure 2
CL, DI: Figure 2
CE, CL: Figure 2
CE, CL: Figure 2
CE, CL: Figure 2
CL: Figure 2
CL: Figure 2
CE, CL, DI: Figure 2
CE, CL, DI: Figure 2
INH, CE: Figure 3
min
typ
max
Unit
3.0
6.0
V
2/3 VDD
1/3 VDD
VDD
V
VDD
0.8 VDD
6.0
V
0
0.2 VDD
V
270
kΩ
100
pF
25
50
100 kHz
160
ns
160
ns
160
ns
160
ns
160
ns
160
ns
160
ns
160
ns
160
ns
10
µs
Electrical Characteristics for the Allowable Operating Ranges
Parameter
Symbol
Conditions
min
typ
max
Unit
Hysteresis
Input high-level current
Input low-level current
Output high-level voltage
Output low-level voltage
Output middle-level voltage*
Oscillator frequency
VH
IIH
IIL
VOH1
VOH2
VOH3
VOL1
VOL2
VOL3
VMID1
VMID2
VMID3
VMID4
VMID5
fOSC
IDD1
IDD2
CE, CL, DI, INH
CE, CL, DI, INH: VI = 6.0 V
CE, CL, DI, INH: VI = 0 V
S1 to S51: IO = –20 µA
COM1 to COM4: IO = –100 µA
P1 to P12: IO = –1 mA
S1 to S51: IO = 20 µA
COM1 to COM4: IO = 100 µA
P1 to P12: IO = 1 mA
COM1 to COM4: 1/2 bias, IO = ±100 µA
S1 to S51: 1/3 bias, IO = ±20 µA
S1 to S51: 1/3 bias, IO = ±20 µA
COM1 to COM4: 1/3 bias, IO = ±100 µA
COM1 to COM4: 1/3 bias, IO = ±100 µA
OSC: ROSC = 270 kΩ, COSC = 100 pF
Power-saving mode
VDD = 3.0 V, outputs open, 1/2 bias, fOSC = 50 kHz,
control data CU = 0
0.1 VDD
V
5.0 µA
–5.0
µA
VDD – 1.0
VDD – 1.0
VDD – 1.0
V
1.0
1.0 V
1.0
1/2 VDD – 1.0
2/3 VDD – 1.0
1/3 VDD – 1.0
2/3 VDD – 1.0
1/3 VDD – 1.0
40
1/2 VDD + 1.0
2/3 VDD + 1.0
1/3 VDD + 1.0 V
2/3 VDD + 1.0
1/3 VDD + 1.0
50
60 kHz
5
70
140
IDD3
VDD = 6.0 V, outputs open, 1/2 bias, fOSC = 50 kHz,
control data CU = 0
200
400
IDD4
VDD = 3.0 V, outputs open, 1/3 bias, fOSC = 50 kHz,
control data CU = 0
80
160
Current drain
IDD5
VDD = 6.0 V, outputs open, 1/3 bias, fOSC = 50 kHz,
control data CU = 0
250
500
µA
IDD6
VDD = 3.0 V, outputs open, 1/2 bias, fOSC = 50 kHz,
control data CU = 1
30
60
IDD7
VDD = 6.0 V, outputs open, 1/2 bias, fOSC = 50 kHz,
control data CU = 1
130
260
IDD8
VDD = 3.0 V, outputs open, 1/3 bias, fOSC = 50 kHz,
control data CU = 1
40
80
IDD9
VDD = 6.0 V, outputs open, 1/3 bias, fOSC = 50 kHz,
control data CU = 1
150
300
Note: * Excluding the bias voltage generation divider resistors built into the VDD1 and VDD2. (See Figure 1)
No.5252-3/17
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