LH532600 查看數據表（PDF） - Sharp Electronics

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LH532600

CMOS 2M (256K × 8/128K × 16) MROM

Sharp Electronics 

CMOS 2M MROM

LH532600

A16 32

A15 33

A14 34

A13 35

A12 36

A11 37

A10 38

A9 39

A8 40

A7 2

A6 3

A5 4

A4 5

A3 6

A2 7

A1 8

A0 9

MEMORY

MATRIX

(262,144 x 8)

(131,072 x 16)

COLUMN SELECTOR

CE 10

CE

BUFFER

TIMING

GENERATOR

SENSE AMPLIFIER

29 D15

27 D14

25 D13

23 D12

20 D11

18 D10

16 D9

14 D8

28 D7

26 D6

24 D5

22 D4

19 D3

17 D2

15 D1

13 D0

OE 12

OE1/OE1/ 1

DC

BYTE 31

OE

BUFFER

BYTE/WORD

SWITCHOVER

CIRCUIT

ADDRESS

BUFFER

29

A-1

NOTE: Pin numbers apply to the 40-pin DIP or SOP.

21

11 30

VCC

GND

Figure 3. LH532600 Block Diagram

532600-3

PIN DESCRIPTION

SIGNAL

PIN NAME

NOTE

SIGNAL

PIN NAME

NOTE

A–1 – A16

Address input

1

D0 – D15

Data output

1

BYTE

Byte/word mode switch

1

CE

Chip enable input

OE

Output enable input

OE1/OE1/DC Output enable input

2, 3

VCC

Power supply (+5 V)

GND

Ground

NOTES:

1. The D15/A–1 pin becomes LSB address input (A–1) when the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to

be HIGH in word mode.

2. Active levels of OE1/OE1/DC are mask-programmable. When DC is selected out of OE1/OE1/DC, it is fixed to an active level. Then it is

recommended to apply either VIH or VIL to the DC pin.

3. DC = Don’t care.

3

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